Model of LM331 for LTSpice

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eTech said:
Simulating the pot is no problem.
Click to expand...

Please provide your concept of simulating the 1M pot to sense from the Standard 0-1v DC range, to higher 0-10v, 0-100v DC ranges, etc., utilizing its switch. When the switch is OFF, the pot's output to V(in) should be at 1M. Once I see a simulating the pot visual plot, parts will be ordered.
link

Finally, can LTspice export the net-list, so the design can be used with Eagle PCB?
Thanks for helping get simulation functional!
 
eTech said:
Frankly, I still don't know what your trying to design.
Click to expand...
My goal is to design a poor man's, software driven, digital storage scope.
I have attached the resistive voltage divider front end to the LM331 circuit.
S1, S2, S3, S4, V3, V4, R7, R8 & R9 have been added.

All switches need to be normally open and closing S1, should simulate as before and was fully functional. Opening S1 and closing S2 & S3 increases full scale sensitivity to 0-10v. Opening S3 and closing S4 should now increase full scale sensitivity to 0-100v DC.

Since this is my 1st attempt at simulation, I need help getting LTspice to independently turn ON/OFF the 4 added switches LTspice calls 'Voltage Controlled Switch'.
 

Attachments

  • LM331_Stand-Alone_V-to-F_Converter_Test5v-vd.pdf
    212.1 KB · Views: 336
eTech said:
Rotary Switch model attached. Place the files in the same folder as your schematic.
Add the symbols and statements as shown.
Click to expand...
V(q) must not vary +/-5% between each scale setting!
By increasing R7, R8 & R9 by a factor of 10, V(q) linearity is lost in simulation, please confirm on your rig:

R7=1k, R8=9.09k, R9=90.9k
0-1v in:
p6_p1=0.035 FROM 0 TO 0.035
t1: time=0.0321415 at 0.0321415
t2: time=0.0323274 at 0.0323274
per: (t2-t1)=0.000185933
freq: 1/(t2-t1)=5378.28
t1_q: time=0.0328846 at 0.0328846
t2_q: time=0.0332561 at 0.0332561
per_q: (t2_q-t1_q)=0.000371491
freq_q: 1/(t2_q-t1_q)=2691.85

0-10v in:
p6_p1=0.035 FROM 0 TO 0.035
t1: time=0.0321107 at 0.0321107
t2: time=0.0322966 at 0.0322966
per: (t2-t1)=0.000185896
freq: 1/(t2-t1)=5379.34
t1_q: time=0.032669 at 0.032669
t2_q: time=0.0330415 at 0.0330415
per_q: (t2_q-t1_q)=0.000372448
freq_q: 1/(t2_q-t1_q)=2684.93

0-100v in:
p6_p1=0.035 FROM 0 TO 0.035
t1: time=0.0321046 at 0.0321046
t2: time=0.0322909 at 0.0322909
per: (t2-t1)=0.000186302
freq: 1/(t2-t1)=5367.63
t1_q: time=0.0326635 at 0.0326635
t2_q: time=0.0330357 at 0.0330357
per_q: (t2_q-t1_q)=0.000372244
freq_q: 1/(t2_q-t1_q)=2686.41

R7=10k, R8=90.9k, R9=909k
0-1v
p6_p1=0.035 FROM 0 TO 0.035
t1: time=0.0321396 at 0.0321396
t2: time=0.0323254 at 0.0323254
per: (t2-t1)=0.000185809
freq: 1/(t2-t1)=5381.87
t1_q: time=0.0328827 at 0.0328827
t2_q: time=0.0332541 at 0.0332541
per_q: (t2_q-t1_q)=0.000371394
freq_q: 1/(t2_q-t1_q)=2692.56

0-10v
p6_p1=0.035 FROM 0 TO 0.035
t1: time=0.0321531 at 0.0321531
t2: time=0.032327 at 0.032327
per: (t2-t1)=0.000173884
freq: 1/(t2-t1)=5750.96
t1_q: time=0.0328487 at 0.0328487
t2_q: time=0.0331965 at 0.0331965
per_q: (t2_q-t1_q)=0.000347771
freq_q: 1/(t2_q-t1_q)=2875.45

0-100v
p6_p1=0.035 FROM 0 TO 0.035
t1: time=0.0321491 at 0.0321491
t2: time=0.0323219 at 0.0323219
per: (t2-t1)=0.000172831
freq: 1/(t2-t1)=5785.99
t1_q: time=0.0328412 at 0.0328412
t2_q: time=0.0331871 at 0.0331871
per_q: (t2_q-t1_q)=0.00034586
freq_q: 1/(t2_q-t1_q)=2891.34
 

Provide your input signal level vs scale settings to use for tests. So we work from the same test values.
 
eTech said:
Provide your input signal level vs scale settings to use for tests. So we work from the same test values.
Click to expand...
Please post your '.asy' battery symbol 'V1' you use in schematic . The LTspice mac version lacks it, along with tool bar/ help menu.
Also, is there a part number/visual for rotary switch S1?

1) R8=1k, R7=9.09k, R5=90.9k (1% metal film)
0-1v scale, .125v DC sig:
p6_p1=0.035 FROM 0 TO 0.035
t1: time=0.0321415 at 0.0321415
t2: time=0.0323274 at 0.0323274
per: (t2-t1)=0.000185933
freq: 1/(t2-t1)=5378.28
t1_q: time=0.0328846 at 0.0328846
t2_q: time=0.0332561 at 0.0332561
per_q: (t2_q-t1_q)=0.000371491
freq_q: 1/(t2_q-t1_q)=2691.85

0-10v scale, 1.25v DC sig:
p6_p1=0.035 FROM 0 TO 0.035
t1: time=0.0321107 at 0.0321107
t2: time=0.0322966 at 0.0322966
per: (t2-t1)=0.000185896
freq: 1/(t2-t1)=5379.34
t1_q: time=0.032669 at 0.032669
t2_q: time=0.0330415 at 0.0330415
per_q: (t2_q-t1_q)=0.000372448
freq_q: 1/(t2_q-t1_q)=2684.93

0-100v scale, 12.5v DC sig:
p6_p1=0.035 FROM 0 TO 0.035
t1: time=0.0321046 at 0.0321046
t2: time=0.0322909 at 0.0322909
per: (t2-t1)=0.000186302
freq: 1/(t2-t1)=5367.63
t1_q: time=0.0326635 at 0.0326635
t2_q: time=0.0330357 at 0.0330357
per_q: (t2_q-t1_q)=0.000372244
freq_q: 1/(t2_q-t1_q)=2686.41

2) Divider values have increased by a factor of 10, in hopes of less loading on testing device
R8=10k, R7=90.9k, R5=909k (1% metal film)
0-1v scale, .125v DC sig:
p6_p1=0.035 FROM 0 TO 0.035
t1: time=0.0321396 at 0.0321396
t2: time=0.0323254 at 0.0323254
per: (t2-t1)=0.000185809
freq: 1/(t2-t1)=5381.87
t1_q: time=0.0328827 at 0.0328827
t2_q: time=0.0332541 at 0.0332541
per_q: (t2_q-t1_q)=0.000371394
freq_q: 1/(t2_q-t1_q)=2692.56

0-10v scale, 1.25v DC sig:
p6_p1=0.035 FROM 0 TO 0.035
t1: time=0.0321531 at 0.0321531
t2: time=0.032327 at 0.032327
per: (t2-t1)=0.000173884
freq: 1/(t2-t1)=5750.96
t1_q: time=0.0328487 at 0.0328487
t2_q: time=0.0331965 at 0.0331965
per_q: (t2_q-t1_q)=0.000347771
freq_q: 1/(t2_q-t1_q)=2875.45

0-100v scale, 12.5v DC sig:
p6_p1=0.035 FROM 0 TO 0.035
t1: time=0.0321491 at 0.0321491
t2: time=0.0323219 at 0.0323219
per: (t2-t1)=0.000172831
freq: 1/(t2-t1)=5785.99
t1_q: time=0.0328412 at 0.0328412
t2_q: time=0.0331871 at 0.0331871
per_q: (t2_q-t1_q)=0.00034586
freq_q: 1/(t2_q-t1_q)=2891.34
 


Which divider values are you going to use? Otherwise, you can make these changes yourself and rerun the tests.

The battery symbol is in the Misc symbol group.

There is no part number for the rotary switch. You'll have to find one.

In addition to the LM331 model, you are using a FF that does not exhibit all the behavior of a real FF.
Keep in mind, you are probably at a point where you'll need to do further testing using real hardware.
Simulation is not a replacement for that.
 
eTech said:
Which divider values are you going to use? Otherwise, you can make these changes yourself and rerun the tests.
Click to expand...
I've simulated two different divider values that only showed skew using these parameters:
Divider values have increased by a factor of 10, in hopes of less loading on testing device.
[R8=10k, R7=90.9k, R5=909k] (1% metal film)

I'd prefer using these higher ohm resistors, if simulation skew can be resolved using SPICE.
What simulation results did you get using these higher ohm resistors, using both 9v and 5v Vs?
 
I changed the square wave rise time to 1uS and set measurement param TD=106mS. This looks better.



Log file:

Direct Newton iteration for .op point succeeded.
.step n=1
.step n=2
.step n=3


Measurement: p6_p1
step p6_p1 FROM TO
1 0.12 0 0.12
2 0.12 0 0.12
3 0.12 0 0.12

Measurement: t1
step time at
1 0.10655 0.10655
2 0.106553 0.106553
3 0.106536 0.106536

Measurement: t2
step time at
1 0.106729 0.106729
2 0.106732 0.106732
3 0.106715 0.106715

Measurement: per
step (t2-t1)
1 0.000179364
2 0.000179229
3 0.000179165

Measurement: freq
step 1/(t2-t1)
1 5575.26
2 5579.46
3 5581.44

Measurement: t1_q
step time at
1 0.107091 0.107091
2 0.107276 0.107276
3 0.107259 0.107259

Measurement: t2_q
step time at
1 0.107456 0.107456
2 0.107643 0.107643
3 0.107624 0.107624

Measurement: per_q
step (t2_q-t1_q)
1 0.000364989
2 0.000366379
3 0.000365791

Measurement: freq_q
step 1/(t2_q-t1_q)
1 2739.81
2 2729.41
3 2733.8

Measurement: vsig
step MAX(v(sig)) FROM TO
1 12.5 0 0.12
2 1.24999 0 0.12
3 0.125 0 0.12

Measurement: vin
step MAX(v(in)) FROM TO
1 0.124758 0 0.12
2 0.124765 0 0.12
3 0.125 0 0.12
 
eTech said:
Which divider values are you going to use? Otherwise, you can make these changes yourself and rerun the tests.
Click to expand...
Updated schematic, using functional divider, as indicated.
Also, I don't see a node labeled 'ear' in schematic that's mentioned in the added '.meas' directive's.
Please interpret attached error that gets flagged after hitting run . . .
 

Attachments

  • V-F_Divider_ERROR.pdf
    3.5 MB · Views: 328
fritual said:
Updated schematic, using functional divider, as indicated.
Also, I don't see a node labeled 'ear' in schematic that's mentioned in the added '.meas' directive's.
Please interpret attached error that gets flagged after hitting run . . .
Click to expand...

specify the model name in the “Value” attribute of each switch symbol.

sw_1P2T

or

sw_2P2T

as appropriate for each switch.
 
eTech said:
Which divider values are you going to use? Otherwise, you can make these changes yourself and rerun the tests.
Click to expand...

Increased divider values showing stable 'freq', but unstable 'q'. Shouldn't 'q' be exactly half 'freq'?
Log show's 'q' error's, too, so would you know the cause?
I added a transistor to gain the forward voltage drop across emitter-base, to give 'ear' a boost. Changed Vhigh to 4v, TTL level.
Finally, I corrected a miss-wire in your schematic, unless this was intentional.
 

Attachments

  • LM331_Stand-Alone_V-to-F_Converter_Test5v-vd-sw-ear.zip
    283.8 KB · Views: 379
Increased divider values showing stable 'freq', but unstable 'q'. Shouldn't 'q' be exactly half 'freq'?
Click to expand...

In theory, yes. but the calculations are based on the output period which includes variances like rise time. So there will be a slight difference. This is why you need to test this in hardware.

Log show's 'q' error's, too, so would you know the cause?
Click to expand...

I don't see any errors in your log file

I added a transistor to gain the forward voltage drop across emitter-base, to give 'ear' a boost. Changed Vhigh to 4v, TTL level.
Click to expand...

Be aware that the actual output level of a real FF device will be based on the supply voltage and will be slightly lower than the supply voltage. Check the FF datasheet.
BTW- 74HC operates at CMOS levels. 74HCT operates at TTL levels.

Finally, I corrected a miss-wire in your schematic, unless this was intentional.
Click to expand...

My schematic is correct. RL should be in parallel with CL.

In addition,
I'm posting a modified schematic that has a few simulation changes to make the measurements more flexible and speed up the simulation time. I've placed dotted boxes around the changes. I hope I didn't miss any. Update your schematic.

 
Last edited:
eTech said:
Be aware that the actual output level of a real FF device will be based on the supply voltage and will be slightly lower than the supply voltage. Check the FF datasheet.
BTW- 74HC operates at CMOS levels. 74HCT operates at TTL levels.
Click to expand...
Attached original V-F w/pre-scaler/dip switches, able to handle 0-44Mhz.
Can the 74HCT74 SPICE model mentioned in link below be used in schematic to perfect simulation?
link

link2
 

Attachments

  • scaler.pdf
    1.9 MB · Views: 297
Last edited:
eTech said:
?

No need to do more simulation. You should move to hardware prototyping and testing.
Click to expand...
Scaler.pdf shows the front end to 'sig', using the 74LS90 IC, wired as a divide by 10.
Feeding a 6MHz ttl signal into DUT and selecting dip switch S3-5, 'sig' will see 60Hz.
If LTspice has a 74LS90 model, this theory of mine could easily be validated.
Perhaps better divide-by-ten IC's exit now, but this was designed long before simulation existed.
 

ok...you have enough simulation info you proceed on your own...good luck.
 
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