MOSFET drivers

[pomme]

I am using a power MOSFET as a switch for an inductive load (1H). How do I determine whether or not I need a gate driver?

Thanks

 

[Hero999]

It depends on what you're using to drive the gate which you haven't said.

 

[MikeMl]

For a low-side N-FET, you need to switch the gate from ~0V to ~3xVt (Vt is the Threshold Voltage from the FET data sheet, typically 10V for a non-logic-level FET). The gate driver needs to be able to charge and discharge the gate capacitance rapidly, so the driver must be able to source and sink > 100mA during switching, even though it takes no current to hold the FET On or Off.

 

[pomme]

I'm planning to use a PWM signal from a PLC to drive the gate. Does that mean that I need to determine the current coming from the PLC output?

 

[Diver300]

Are you using the PWM signal to regulate the current in the 1 H load?

A few more details, like the switching frequency, the MOSFET that you intend to use, and the ratings of the PLC output would help.

 

[pomme]

My plan is to have the PWM signal going to the gate of the MOSFET (FDP5800), and the 1H load connected between a +42V battery and the drain - with a free-wheeling Schottky diode across the inductor. PLC output voltage is 24V.

 

[Diver300]

You still haven't said if you are using the PWM signal to regulate the current.

What is the switching frequency?

 

[pomme]

In essence, yes the PWM signal will regulate the current through the load. How do I determine the switching frequency?

 

[MikeMl]

Like I said in my earlier post, it takes a good fraction of an Amp to charge and discharge the gate capacitance of a typical MosFET used as a PWM switch. You will be lucky if the output pin on your FPGA will source/sink more than 20mA at 5V, so a gate driver will be needed.

This circuit drives the gate using a driver made from discrete parts. I used only a 3.3V drive signal to show how the gate is driven with ~10V. You could use a 5V drive with no changes. This circuit charges the gate with ~200mA on the low to high input transition, and discharges the gate with ~180ma on the opposite transition. The purple trace is the power dissipation that occurs in the Fet at each transition.

 

[Hero999]

The arrangement of Q1, D1 and Q2 look familiar.

 

[pomme]

True, my PLC signal would not be able to drive enough current to the gate. I am thinking of using a gate drive optocoupler instead of just a low-side gate driver.