For a low-side N-FET, you need to switch the gate from ~0V to ~3xVt (Vt is the Threshold Voltage from the FET data sheet, typically 10V for a non-logic-level FET). The gate driver needs to be able to charge and discharge the gate capacitance rapidly, so the driver must be able to source and sink > 100mA during switching, even though it takes no current to hold the FET On or Off.
My plan is to have the PWM signal going to the gate of the MOSFET (FDP5800), and the 1H load connected between a +42V battery and the drain - with a free-wheeling Schottky diode across the inductor. PLC output voltage is 24V.
Like I said in my earlier post, it takes a good fraction of an Amp to charge and discharge the gate capacitance of a typical MosFET used as a PWM switch. You will be lucky if the output pin on your FPGA will source/sink more than 20mA at 5V, so a gate driver will be needed.
This circuit drives the gate using a driver made from discrete parts. I used only a 3.3V drive signal to show how the gate is driven with ~10V. You could use a 5V drive with no changes. This circuit charges the gate with ~200mA on the low to high input transition, and discharges the gate with ~180ma on the opposite transition. The purple trace is the power dissipation that occurs in the Fet at each transition.
True, my PLC signal would not be able to drive enough current to the gate. I am thinking of using a gate drive optocoupler instead of just a low-side gate driver.