My Digital clock circuit is not going

[Unknown100]

I'm a very beginner in electronics...Here's my circuit... I have made last three digits of HH:MM:SS clock but the minute SSD(shown) is not working on my simulator...
Please I need help....

 

[crutschow]

That's like asking, "my car is not running, what's the problem?".

How is it not working?

 

[duffy]

Eo from IC1 goes high on a carry, but OE on IC3 is expecting a low to enable counts.

 

[Unknown100]

Duffy,
To enable count, i've set CE low...same is in IC1...there it works
And what is OE? I didn't get you...
Actually my problem is that, when the terminals A,B,C goes low, this must give an o/p high. and this high is fed into clk if IC3.....While simulating the o/p comes as high as expected but clk shows 0.....

 

[Unknown100]

View attachment 60353

This is, while i run my simulator

 

[duffy]

You have EO grounded on IC3. This is an output and should not be grounded.

 

[Unknown100]

Ya i've removed the ground from EO now.....but not working still now...Is my logic right? ....Please suggest some alternatives for a digital clock using 4000 series ICs

 

[Boncuk]

Hi,

this is not a digital clock as you consider your design to be it.

It is a simple up/down counter circuit counting up and down from 0 to 999 and recycle.

To load indiviual settings to the tens and hundreds repeat the circuit used for the ones.

Boncuk

 

[Unknown100]

**broken link removed**

I've not thought of circuit further than this..This pic shows two second SSDs and one minute SSD..
I am trying to reset the mid SSD's counter when its value is 6...............
Please Help me people.... And i am unnown of further circuits as well

 

[RDL2004]

Take a look at this project. It may help you out.

**broken link removed**

here is the schematic.

oldradiobuilder.com LED Wristwatch .pdf

 

[Unknown100]

Thankyou so much man....... But have you tried this schematic.....
OK I'll try it

 

[audioguru]

You are combining TTL with Cmos logic. But the minimum TTL logic high output voltage is not high enough for a Cmos minimum logic high input voltage according to Don Lancaster in his Cmos Cookbook. He suggests adding a 2.2k pullup resistor to make the logic high output voltage from the TTL output high enough.

But your Simulator program probably doesn't know these things.

 

[Unknown100]

oh oh.....is that the problem..... thanks brother....i actually didn't knew about pull up resistors........
can you show a demo circuit to use pullup in my circuit........
Is it like switch?......which will be On when cmos o/p CLK is on and provides TTL sufficiently high valued trigger...?

thanks in advance brother

 

[audioguru]

TTL logic ICs operate only with a +5.0V supply.
The minimum output high voltage of a TTL gate is +2.4V and is +2.7V for an LS-TTL gate.
The minimum input high voltage of a Cmos gate is +3.5V.
So the voltage must be higher for it to be recognized as a valid logic high voltage.

The 2.2k pullup resistor "pulls up" the voltage because it is connected to the +5.0V supply.
It is shown here:

 

[Unknown100]

thanks brother it's working now.........
My clock is now complete upto MM:SS.....
For the HH part i've not thought yet.....
If any problem, i'll be back here....
Thanks again

 

[Unknown100]

How can I use pin 14 and C-out of 4026 in HH.....?
I mean using flipflop with these two and hit reset to the 10s of HH.....