Need help with fixing my circuit design.

Can you measure the voltages on the CL line when it is connected to the logic gates? What is the voltage when the state is 011 and what is the voltage in any other state?

If the input to any of the 4000 series ICs is floating you will get unpredictable results.

You are mixing 4000 series and 74LS series logic gates. The inputs to the 74LS logic gates pull up with a current of 0.4 mA and need quite a low voltage, less than 0.8 V, to guarantee a low level. You should check that you are getting a voltage that low.

CMOS ICs can appear to work fine, and will work fine in some conditions, with power rails not connected. Those are worth checking.

You need to decouple the power supplies with suitable capacitors for each IC.

The clear and load on this are asynch, so when counter reaches that state the
state lasts for only gate prop delays. So one must look at setup and hold times
of the CL and LD inputs to make sure counter behaves logically.

Info here on issue : https://learn.saylor.org/mod/book/view.php?id=27103&chapterid=3246


Regards, Dana.

Counting from 1010 (0x0A0) to 0011 (0x03) means passing through zero with a continuous count; you should not be using the clear input at all???

The reload should occur on the next clock after 0011, if that is the last valid state.

With an async load, decode 0100 to cause a load.

Doing that with a counter that does not have a synchronous will mean you get a glitch, a very short 0100 state until the load takes effect.

That may also be breaching the "synchronous counter" requirement you state at the start of the post.


A 74163 (or LS or HC or HCT163) would be more appropriate, as that has a synchronous load.
For that you would just decode 0011 and at the next positive clock edge it would take the value from the preset input pins, rather than incrementing.

That would be glitch free and no timing issues.

Is this coursework or homework?