NiCad Battery Testing

[MikeMl]

...I have something else that I don't understand in the same circuit. It also appears in both Mike DC and my transient analysis.

Using Mike's DC analysis, at any point when Vb >~1.2V, Vg = 3.0V. The FET should be off, but -Ib still shows 250mA of current flow. (the same thing is seen in the transient analysis while Vb>1.0*n) So either what am I missing, or why???

Maybe this will help. I converted my sim to a .TRAN time-based sim. I model the battery being discharged as a 1000Farad capacitor initially charged to 4V. I simulate for long enough to see where the battery voltage V(d) finishes up, and I plot V(g) and V(s) to see what they are doing, too.

Note that the circuit works as a constant-current sink while V(d)>V(s) (about 12Ks along the x-axis). In this region, the NFET is not saturated, and V(g) is what it takes to make Id(M1) = 0.25A (as determined by Vref and R4).

Once the simulated battery discharges to where V(d) = V(s), the NFet is saturated, and the opamp vainly tries to increase V(g) to keep V(s) at 1V, but to no avail. With only 5V on the opamp, V(g) cannot go higher than ~4V using an LM358. A rail-to-rail out opamp could go a bit closer to 5V.

Note that this sim shows that the circuit does not stop the battery from being over-discharged as you surmise. In fact, it continues being discharged after the V(d) = 1V point is reached, just not at a constant 0.25A!

 

[ADWSystems]

Note that the circuit works as a constant-current sink while V(d)>V(s) (about 12Ks along the x-axis). In this region, the NFET is not saturated, and V(g) is what it takes to make Id(M1) = 0.25A (as determined by Vref and R4).

In the region, V(d)>V(s) why is Vg not changing with Vd? My simulations show it as constant even though V(d) is dropping and the current is constant.

Since this looks like it may be a very small voltage change in this region, I'm concerned about noise upsetting the regulation of Vs.

 

[MikeMl]

It is changing, but ever so slightly... V(g) is actively driven by the opamp to be "exactly" what it takes for the drain current of the NFet to be 0.25A. V(g) is not particularly noise sensitive because it is driven from the opamp's relatively low output impedance, and besides, it is inside the opamp's feedback loop.

If you are worried about noise, then worry about how clean the 5V supply is. Since the reference voltage is derived directly from the 5V supply, then any noise on it gets inside the feedback loop. Putting a bypass cap at the non-inverting input of the opamp would help...

 

[ADWSystems]

OK. Last item (I think, or for now). But Mike started it. Jumping back to the DC analysis and working with the 4 ohm 250mA constant current source. What power is dissipated by the FET when discharging 10 cells from 12V to 10V at 250mA, if Vs is set to 1V?

My initial thought, that feels as right as it does wrong, would be 11V to 9V (12V to 10V - 1V Vs) at 250mA or starting st 2.75W with Vd=12V and dropping to 2.25W when Vd=10V. So the FET is doing the bulk of the work, because the 4ohm resistor is only (and always) dissipating 0.25W (1V @ 250mA).

 

[MikeMl]

Being lazy, I'll ask LTSpice to do it for me...

I pre-charge the simulated battery to 12V. It takes 8Ks to discharge it to 10V. The power dissipated in M1 is shown as the yellow trace; 2.742W @ 12V and 2.245W @ 10V. LTSpice knows how to do this intrinsically just by placing a special cursor over the component in question in the schematic. You can place cursors in the resulting plot to see the detailed values under the cursors.

 

[ADWSystems]

So the FET is doing the bulk of the work, dissipating most of the wattage.

If there were a few "options" (R4 and Vref combinations) then some of the load could be shed from the fet to the resistor bank. It just means that Vs will increase which should be fine, if I provide enough Vcc headroom. My 6 cell simulation shows a Vg of 7.6V while powered from a 10V source. How much headroom (Vg to Vcc) would be enough?

Can the FETs be paralleled to share the load?

 

[MikeMl]

So the FET is doing the bulk of the work, dissipating most of the wattage.

If there were a few "options" (R4 and Vref combinations) then some of the load could be shed from the fet to the resistor bank. It just means that Vs will increase which should be fine, if I provide enough Vcc headroom. My 6 cell simulation shows a Vg of 7.6V while powered from a 10V source. How much headroom (Vg to Vcc) would be enough?

Depends on the opamp. An LM358 operated from 12V will pull-up to about 12V-1.6v = 10.4V. A more R-to-R one would pull higher.... I told you before that V(g) ~= V(s) + Vth + a few tens of mV.

Can the FETs be paralleled to share the load?

How many 80W NFets do you need to parallel to handle 2.5W? I'd say just one, but it needs a heatsink, even if it is in a TO-220 package.

 

[ADWSystems]

I forgot about the opamp rails.

I didn't correlate this aspect of the circuit to the wattage rating of the FET. My bad. Now off to refresh myself on spec'ing heatsinks...