not gate oscillator

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Hero999 said:
Be patient, it's getting late here and I'm off to bed.

I'll answer your question tomorrow, providing I've not been banned for the fight I had yesterday in another thread, I assume EM hasn't seen it yet.
Click to expand...


HA! That was no fight. You should have seen what went on while you were on your hiatus
 
All right, as expected I've been banned for two years. It was longer than expected but it's probably a good thing. I've been posting here far too much recently.

Anyway, I promised to help you with this and that's what I'm going to do.

As far as D1 is concerned, it triggers the timer.

When T2 is off it doesn't do anything, when T2 turns on it takes the input to gate 4 low thus triggering the timer.

Sorry, I can't spend longer on this post, I don't want to be banned again before I get chance to press the the post button.
 
Hero999 said:
Be patient, it's getting late here and I'm off to bed.

I'll answer your question tomorrow, providing I've not been banned for the fight I had yesterday in another thread, I assume EM hasn't seen it yet.
Click to expand...

Why D1? Why it is reversed?
anyone help
thanks
 
D1, gate 4, C7, R7, R6 and gate 3
determine how long the intermitten beeping is gonna last.
You can call it a time buffer.

When gate 3 out is high (and it initialy is because of r7)
gate 4 in is high and out is low and gate 3 in is low so
the mentioned circuit is in stable state and there is no beeping.

Now t2 pulls gate 4 in low and it is crutial that r4 doesn't
pull it high prematurely (thus d1).

Now C7 is charging and while it is charging portion of the circuit in question
is in quasy stable state: voltage on r7 is high thus 3 in is high, 3 out and 4 in are low.
R4 would disable this low 4 in if it wasn't for the d1 (and would disable the qstable state).

when c7 charging is done 3 in goes low and we are back to stable state.
Another set of beeping will not accure until c7 discharges
(since 4 out is low c7 is in parallel with r7 and it is discharging)

Please feel free to trash talk me if I am wrong cause I spent some time on this...
 
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vlad777 said:
When gate 3 out is high (and it initialy is because of r7)
gate 4 in is high and out is low and gate 3 in is low so
the mentioned circuit is in stable state and there is no beeping.
Click to expand...
Can I conclude from this that the first oscillator composed of gates 5 and 6 is enabled when logic zero is applied to the in terminal of gate 6, and disable when logic one is applied to that terminal?
What about the case when no Whistling voice? isn't the same and the oscillator should enable?

Now t2 pulls gate 4 in low and it is crutial that r4 doesn't
pull it high prematurely (thus d1).
Click to expand...
I still did not understand the role of D1?

We have two cases, (1) when no Whistling voice, now there is only a DC voltage at the cathode of D1 and D1 will prevent DC. Now at this moment why gate 3 out and gate 4 in are high?
Case (2) when a Whistling voice is sensed, now there there are a DC voltage + the amplified ac signal at the cathode of D1 and D1 will prevent DC permitting only the negative part of the ac signal. That negative part of the ac signal will make the gate 4 in low. Is that true??
Thank you vlad777 very much, I hope to continue discussing this topic with me.
 
walid66 said:
Can I conclude from this that the first oscillator composed of gates 5 and 6 is enabled when logic zero is applied to the in terminal of gate 6, and disable when logic one is applied to that terminal?
Click to expand...

Yes.

What about the case when no Whistling voice? isn't the same and the oscillator should enable?
Click to expand...

R7 grounds 3 in

I still did not understand the role of D1?
Click to expand...

4 in is low for the period of beeping and if it wasn't for d1, r4 would not allowe this.

We have two cases, (1) when no Whistling voice, now there is only a DC voltage at the cathode of D1 and D1 will prevent DC. Now at this moment why gate 3 out and gate 4 in are high?
Click to expand...

because of r7 that makes 3 in low (and there is no current trough c7 )


Yes. I think that actualy only the first negative part is needed for trigering.
 
Hero999 said:
....
There must be a way to stop it from self triggering, i.e. when it's beeping it doesn't hear its own beep, I assume it detects a different frequency whistle than the sound it produces.
Click to expand...

Sorry to disagree with a member that no longer has the aportunity to answer...

The circuit should filter out human whiseling but the reason it does not trigger it self
is not because of the frequencey but the circuit is not responsive until c7 is discharged.
 
I'll come to the aid of that member. C1 and C2 are high pass filters, which keep the lower "beep" frequency from self-triggering the circuit. C7 only determines the duration of the beep-beep.
 
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There is a keys finder project on another website. Its piezo transducer is its beeper and its "microphone". It resonates at 4kHz where it beeps very well but has a very low output at 2.5kHz which is the highest frequency I can whistle.
 
BrownOut said:
I'll come to the aid of that member. C1 and C2 are high pass filters, which keep the lower "beep" frequency from self-triggering the circuit. C7 only determines the duration of the beep-beep.
Click to expand...

Maybe I am wrong but I calculate 4.8 kHz frquencey for the last stage.
 
To vlad777

Thank you vlad777 for these more than wonderful answers, which helped to clarify the picture dramatically.To complete the picture I have more questions, I hope that you have the time to answer them:
(1)
Thats a very good point, but are you mean: "until c7 is discharged" or until it is fully charged, then gate 3 out become high?
(2) For the first oscillator (gates 6 & 5) R8 = 1M and C8 = 100n, the o/p freq = 7 Hz, and the second oscillator (gates 1 & 2) R5 = 1M and C5 = 100p, the o/p freq = 7 KHz. The two osci's are in active for 2.42 sec. Number of cycles the 1st osc. produce in that period = approx 17 cycles, half of these the 2nd osc is ON and oFF in the other half, So, 8 times the 2nd osc can beep with 7kHz tone, not only two beep as other member said?
(3) Why Diodes D3 &D7, how it pass the logic zero from timer to osci?

To BrownOut,

Thank you for your participation
I'll come to the aid of that member. C1 and C2 are high pass filters, which keep the lower "beep" frequency from self-triggering the circuit. C7 only determines the duration of the beep-beep.
Click to expand...
(1) I searched the internet for frequency of human whistle and found that it is between 1800 to 2100 Hz. If that is true then the 1st high pass filter (C1 + Zin of the 1st stage) will block that freq.
I calculate Zin = 45 Kohm, so the cutoff freq = 3500 Hz which is far from 2000 Hz. Are you advice me to rechoose C1?
(2) C2 makes with any part of the potentiometer the othe HPF?

To my best teacher and friend audioguru:

There is a keys finder project on another website. Its piezo transducer is its beeper and its "microphone". It resonates at 4kHz where it beeps very well but has a very low output at 2.5kHz which is the highest frequency I can whistle.
Click to expand...
That was A very good point, and I think it is the main problem preventing the circuit from working well.
I need to know: is the freq of human whiseling is 2kHz or 4kHz?
If it is 2kHz, is it true to modify all the caps that precede D1?
Thank you very much
 
But the human whistle is at a much lower frequency than a piezo transducer can detect when it is a microphone.
 
(1)
When c7 is fully charged r7 voltage drops (no current no voltage) and 3 out goes high,
but after that it needs to discharge. So now 4 out is low which means c7 and r7 are in parallel
(c7 is discharging trough r7) and 3 in voltage is negative (since the + side of c7 is grounded).

Whistleing at it when c7 is full will give no result.

(2)
(I thought c5 was 150 pF) The time the "time buffer" is on or off depends on R7C7
and how full is c7 when triggered. (but I don't know the exact formula, how did you get 2.42 sec)
Don't understand "in active", is it: not active ,inactive or in operation?

(3)
D3 & D7 are there to prevent next stage to influence previous stage. (look at #9 post)
 
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That was a very good answer, I understand very well, thanks

Time constant = 1.1 *R7 * C7 = 2.42 sec, I think so, please correct me.
in active = in operation = enabeled
(3)
D3 & D7 are there to prevent next stage to influence previous stage. (look at #9 post)
Click to expand...
yes I get it.

Please vlad777 try to answer the two questions i asked to To BrownOut, at #35 post
thank you alot

To audioguru:
But the human whistle is at a much lower frequency than a piezo transducer can detect when it is a microphone.
Click to expand...
If I replaced it with an original speaker, what should the modification in that part of the circuit be?
thank you very much
 
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