NPN transistor as an amplifier

I need help designing a multi-stage amplifier with a gain of 30, a load of 4 Ohms, and a maximum imput signal of 10 mVpk. There should be a output swing of 300mVpk while driving the load impedance. The amplifier input impedance must be > 50 kOhms. The supply must be 3 V. I will be using NPN 2222-type transistor for this task. I must not use more than 3 stages but in the last stage I could use up to 5 transistors connected in parallel.

Any hints on how to start? I was told to start backwards.

So far I am working on the last stage using a common-emmtier confuguration (buffer) but my output saturates on the negative swing when I use a 300 mVpk input signal (that is what I want as an output).

Thanks,
Ed

7. Finished - that was easy.
6. DC couple it to the emitter-follower output transistors.
5. "H" layout (also called an H-Bridge) a common emitter transistor with a gain of 30
4. Connect them as emitter followers.
3. You have to work out how many 2N ... you are going to use.
2. You have to realise the current is too much for one 2N......
1. You have to work out the current though the 4R load resistor.

This is a good book that explains how most of this works:

https://www.amazon.com/Electronic-P...8333/ref=sr_1_1?ie=UTF8&qid=1311401440&sr=8-1

You can get it used for $12. Even though it is not the latest edition, the basics haven't changed and it is worth every penny.

Everything you need to know is on the web FOR FREE!

I am still having difficuty with the design. I am working with PSpice to simulate the circuit and it is not giving me the gain I want. How does one achieve a gain of 30 using 3 stage amplifier?

1. It is not a 3-stage amplifier.
2. It is a 2-stage amplifier.
3. The voltage gain of the emitter-follower stage is 1.
4. Put 1k in the emitter and 30k in the collector of the H-bridge and the gain is 30.

Lalo79 said:

I am still having difficuty with the design. I am working with PSpice to simulate the circuit and it is not giving me the gain I want. How does one achieve a gain of 30 using 3 stage amplifier?

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I would use 2 NPN transistors as 2 common emitter amps, easily giving you the gain of 30.

Then an output stage to drive 300mV p/p into 4 ohms is pretty easy, 0.3v/4ohms is only 75mA so you can use a single transistor in emitter follower mode, class a driving the speaker through a coupling capacitor.

It sounds like a basic classroom assignment? Please show your circuit, it shouldbe easy enough to re-bias your output stage to stop it saturating.

I took it as a 4ohm load such as speaker and allowed for 300mV swing around a mid point of 1.5v. That's why the question is not detailed enough. It does not specify the output biasing.
You will need 2 transistors in DARLINGTON to get 50k input impedance in an H biasing network to get a gain of 30 and an emitter follower on the ouput that is biased due to the DC coupling from the first stage. You have got the value of one resistor already 50k or higher. You can work out all the rest provided you know the quiescent output voltage.

colin55 said:

You will need 2 transistors in DARLINGTON to get 50k input impedance in an H biasing network to get a gain of 30 and an emitter follower on the ouput that is biased due to the DC coupling from the first stage.

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What?!?!?

As Mr. RB points out, you can easily get a gain of 30 from two simple common-emitter stages.

Honestly, I don't know where you come up with this stuff. For a smart guy who knows electronics, you come with some pretty wild answers.

Listen Carbonzit. I have had enough of your ignorance and rudeness - even throught your PM's to me.
How are you going to get 50k input impedance with a single common emitter stage?

wow!! This is a little over the top of my head. This is new to me so can you explain things a little bit simpler please. First , I don't think i can use a H bridge since I was not told to use it and it is the first time hearing about it. I was suggested to be 500 mV above ground for the bottom swing and 1.2 V below the top (3V). I guess I am not seen how gain will occur in two stages. What will be the resistors that will dictate the gain? How does the gain from the first stage affect the gain of the second stage? is gain added or multiplied? Theese questions might be ignorant questions but I am truly trying to understand this material. Thanks for replying

To start with, you have been given a reasonably complex task. The parameters were not fully provided and I designed the amplifier on a completely different basis to RB.
To get a specified gain from a stage you need an emitter resistor and collector resistor (load). To turn on the base you need a voltage divider and these 4 resistors form the legs of the letter H. That’s how they get the name “H-bridge”
I tried to get the amplifier sitting somewhere at mid-rail - which is the normal thing to do, whereas RB had it sitting on the floor.
If it were an easy task, you would have had dozens of replies already. It’s like a Suduko puzzle with lots of numbers missing.
Now you come up with the biasing of the input.
It has to be 700mV above ground or you will get “cut-off.”
As I said, you need Darlington input to get 50k.
Work out your H-bridge for 30x gain and connect the emitter follower to the collector.

colin55 said:

Listen Carbonzit. I have had enough of your ignorance and rudeness - even throught your PM's to me.
How are you going to get 50k input impedance with a single common emitter stage?

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Regarding the input impedance, I guess I overlooked that aspect of the O.P.'s requirements, so I owe you an apology. Here it is: sorry I said those things.

To get 50KΩ input impedance, they'll need to use either a CC (aka emitter follower) or a Darlington stage as you suggested. (According to my textbook, you can only expect to get about 3KΩ with a CE amplifier.) While an emitter follower would probably work, it wouldn't be the first choice, as it has no gain (well, unity gain). So a Darlington it is. (Mr. RB, if you're reading this, do you agree that your solution wouldn't provide a high enough input impedance?)

Regarding my PMs to you, yes, I recall a whole string of them a while ago when I was researching on of your circuits (a boost converter running on 3 volts, which is still an intriguing circuit to me, even though I never got it to work as well as you claimed it did). I still have them in my inbox and outbox.

Since you brought this up in this public forum, all I can say is that while you did provide me some information, for which I am grateful, I found it very frustrating trying to get answers to questions from you, as your replies were invariably only 4 or 5 words, and I kept having to ask you more questions. Now, you could have replied more fully, or you could have said "Don't bother me anymore!", at which point I would have respected your wishes.

But if you're going to give people answers to questions, as happens here, it's better to give an explanation, rather than just say "Do this" or "Do that" without explaining why you should do this or that.

Regarding my ignorance, yes, I freely admit that I am ignorant of a lot of aspects of electronics. That's why I hang out here! to try to fix my ignorance. (I do have some knowledge, which I'm glad to share with others.)

I guess that's the end of my Sunday sermon.

This is what I have as a buffer (Third stage) so far but the input impedance of it is around 536 Ohms according to my calculations. How do you reach 50 KOhms impedance if anything connected to the buffer will be in parallel to it and thus making the total impedance less than 536 Ohms. I am still confused as to what put as the values for the Common Collector since that is what it is going to provide the gain.

I forgot to mention that there is one more parameter I need to worry about and that is that the multi-stage amplifier must be linear such that the harmonic distortions are maintain below -25 dB for an output swing of 300 mVpk

Lalo79 said:

I forgot to mention that there is one more parameter I need to worry about and that is that the multi-stage amplifier must be linear such that the harmonic distortions are maintain below -25 dB for an output swing of 300 mVpk

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That's an odd way to specify distortion: generally speaking, distortion is rated as a percentage (total harmonic distortioN--notice it's singular, not plural--or THD) of the amplifier's output, not in dB.

Here is a start to the type of circuit you need:

**broken link removed**

Colin,
I tried your first schematic (minimum values) and most of the values are closed but not at the output. I have ac couple the input, the middle section of the transistors (separating the CC from the buffer), and the output. For the output I have put in the emmiter side an additional resistor in parallel with both a capacitor and the load (4 Ohms) which are in series. How can this work? Is there any way for this working?

I think Colin intends for the circuit to be used exactly as drawn (with the possible exception of input and output coupling capacitors to remove DC). No need for inter-stage capacitors. Colin?

I have to say, Colin, that that is a very good graphic explanation you gave up there.

carbonzit said:

...
So a Darlington it is. (Mr. RB, if you're reading this, do you agree that your solution wouldn't provide a high enough input impedance?)
...

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I took the original question as a "classsroom challenge" type of thing where everything has to be pushed to the limit to barely meet the specs. I also assumed (in line with that thinking) that the OP meant "3 stages" of 2N2222, meaning of course 3 transistors in the design (although he allowed for paralleling some output transistors). So it seemed more a challenge of trying to get near those specs with 3 transistors, and audio quality was never mentioned, if at all important the only thing mentioned was 10mV in and 300mV out.

It may not be possible to meet the 50k input impedance with 3 2N2222, but you could try the first CE stage with RE 100k and RC 270k (gain of 2.7) and say 470k for RBH and RBL. 2N2222 has quite high Hfe at such low signals.

Then a second CE at gain of 10 or 11, again pushing the impedance limits but not impossible.

And a final stage emitter follower running say 150mA class A into a low ohms resistor and capacitive coupled to the 4 ohm speaker. Being allowed to parallel the 2N2222 here could allow the gain to be pushed up by choosing current per device to improve the Hfe.

Like I said it sounds like one of those classroom challenges where the specs are deliberately chosen so everything is very close to being possible from 3 transistors, if everything is pushed to the limit and distortion is not an issue...

And of course if distortion is an issue you wouldn't have the silly challenge criteria of only 3 stages and only 2N2222 and paralleling 2N2222 for class A output etc...

Running a sim of the first circuit of post #16 in LTSpice gives a gain of 0.5 ! I think the problem is that the input impedance of the final stage is too low and is shunting the collector load, thus reducing the gain of the darlington stage.