The frequency is within the capability of the device using a timing capacitor of 0.001 to 0.002 uF with resistors in the 3K to 5K range.
e.g. 0.002 uF and 3.83K --> 7.66 usec --> 130,548 Hz.
A dead time of 200 nsec appears to be unrealizable as the shortest time documented is 500 ns with a .001 uF capacitor.
The output is a ramp from 1.5 to 3 Volts with the fall time determinign the dead zone.
This sounds like 7.16 usec on the ramp and 500 nsec dead time.
I think you will be close -- certainly worth experimenting with.
As an LTSpice fan I would encourage you to get the simulator and try it on your PC before investing time and money. Simulators are not the complete answer, but they do provide quick check on a devices capabilities.