PCB Fabrication: Fusion PCB v. Elecrow v. Smart-Prototyping

[ADWSystems]

JonSea: I should has asked or verified this. Regarding the NPTH holes. You have only one "component" for the NPTH, just the drill hole? And you are able to get the one NPTH "component" to show on the mechanical layer and the drill drawing. There is not a hole and a circle on the mechanical layer (two "components"). I have been assuming the latter, but we all knows what happens when someone assumes.

 

[JonSea]

No, nothing special as far as a hole goes. Eagle has the option of placing (unplated) holes or (plated) pads/vias. Both have an entry in the drill file.

I had to make the NPTH layer in the CAM processor. I'm not sure how I learned that including holes but not drills in the layer makes only the non-plated holes.

If the drill file shows them differently you may be able to just highlight which holes are unplated on a print and include it as a pdf.

Dealing with unplated holes in the fab house is a manual operation. All the holes are drilled, then the holes are plated. Non-plated holes are plugged during the plating operation so they don't get plated. The danger of a non-plated hole being plated is that there's no annulus for the plating to hole on to. During sussequent steps, any non-anchored bits of metal may break free and stick someplace else.

It is truly amazing how much work goes into making a 50 cent circuit board!

 

[ADWSystems]

As shown previously, my CAM processor only consists of selecting which gerber files to make. That's it.

Looks like I'm doing this the hard way. Luckily it will only apply to breakoff holes, as I plate (almost) all holes in the board. It looks like I have been being nice to the fab houses.

 

[JonSea]

A good reference is Seeed Studio's PCB DFM Manual, version 1.1 It covers many issues in designing circuit boards.

 

[ADWSystems]

A good reference is Seeed Studio's PCB DFM Manual, version 1.1 It covers many issues in designing circuit boards.

Thanks for the link. I like to have reference materials like that around. It appears to be a single source for the series of disconnected information I have collected and use. I will take a more thorough read through it tomorrow but at first glance, those appear to be the design rules I follow. It doesn't appear to touch on anything we have been discussing (drat!). That could be for a few reasons. They may not have covered, it may not apply to Seeed Studio, or it only applies to Elecrow's process. It does have a nice and clear description of stamp holes for breakaway sections. Which of course would be NPTH, and they don't indicate any special requirements for those (Seeed vs Elecrow)