;REGISTER DECLERATIONS
REG1 EQU 60H ; HERE WE ARE NAMING THE GENERAL PURPOUSE REGISTER
ADC EQU 61H
REF EQU 62H
REG2 EQU 63H
REG3 EQU 64H
REG4 EQU 65H
F EQU 66H
ORG 0000H
;ALL INTIALIZATION HERE OF ALL PORTS AND PERIPHERALS HERE
MOVLW B'00000001' ; SET AN0 AS ANALOG INPUT AND SWITCH ON ADC MODULE
MOVWF ADCON0
MOVLW B'00111110' ;SET AN2 AND AN3 AS REFERENCE VOLTAGES, AND SET AN0 AS ANALOG INPUT
MOVWF ADCON1
MOVLW B'00101100' ;SET AS LEFT JUSTIFIED, SET AS 12 TAD, SET AS FOSC/4
MOVWF ADCON2
CLRF PORTD ;DECLARE PORT D AS OUTPUT FOR THE DIGITAL OUTPUT
CLRF TRISD
MOVLW B'111111' ;DECLARE PORT A AS INPUT FOR THE ANALOG INPYT
MOVWF TRISA
SETF PORTB ;DECLARE PORT B AS INTUP FOR THE REFERENCE SWITCHES
SETF TRISB
CLRF PORTC
CLRF TRISC
CLRF ADC ;CLEAR REGISTER ON START UP ONLY
CLRF PORTC
CLRF REF
;START MAIN PROGRAM HERE
MAIN
;TEST SWITCHES ... DECREMENT AND INCREMENT REFERENCE REGISTER (REF)
BTFSS PORTB,6
BRA LINE9
INCF REF
CLRF PORTD
MOVFF REF, PORTD
CALL DELAY
LINE9
BTFSS PORTB,7
BRA LINE8
DECF REF
CLRF PORTD
MOVFF REF, PORTD
CALL DELAY
LINE8
;ADC ROUTINE
CALL ACQ_DELAY ;CALL DELAY
BSF ADCON0,1 ; CONVERSION IN PROCESS (START CONVERTING)
LINE1
BTFSC ADCON0,1 ;check if ADCON0 bit 1 if clear,if yes skip the next instruction
BRA LINE1
RRNCF ADRESH ;SHIFT RESULT TO THE RIGHT. THIS WAY IT WILL HAVE 7 BITS INSTEAD OF 8 BITS
BCF ADRESH,7 ;CLEAR THE LAST BIT OF REG1. THIS IS DONE SO THAT IF THE SHIFTED BIT IS 1, IT WILL BE CLEARED (0)
MOVFF ADRESH,PORTD ;MOVE VALUE FROM ADRESH REGISTER TO PORTD
;COMPARE ADC RESULT WITH REGISTER 'REF'
MOVFF ADRESH , F
MOVLW REF
CPFSGT ADRESH
BRA LINE7
BRA LINE5
LINE7
BSF PORTC,2
GOTO MAIN
LINE5
BCF PORTC,2
GOTO MAIN
DELAY
CLRF REG2
CLRF REG3
MOVLW 30
MOVWF REG4
BSF PORTC,2
LINE1_DELAY
DECFSZ REG2
BRA LINE1_DELAY
DECFSZ REG3
BRA LINE1_DELAY
DECFSZ REG4
BRA LINE1_DELAY
RETURN
ACQ_DELAY
MOVLW REF
MOVWF REG1
ACQ1
DECFSZ REG1
BRA ACQ1
RETURN
END_OF_PROGRAME