OD EQU 60H
OE EQU 61H
OF EQU 62H
O5 EQU 65H
O6 EQU 63H
COUNT1 EQU 66H
COUNT2 EQU 64H
COUNT3 EQU 67H
table_temp EQU 68H
table EQU 69H
REG1 EQU 70H ;<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
;LCD DISPLAY PINOUTS
;1-GROUND, 2-VDD,
;3- VO(CONTRAST CONTROL)CONNECTED TO GROUND
;4-REGISTER SELECT = RE0 LOGIC 1 IF MICRO IS TRANSFERRING DATA
;LOGIC 0 IF MICRO IS TRANSFERRING A COMMAND
;5-READ/WRITE = RE1 LOGIC 1 TO READ FROM MODULE
; LOGIC 0 TO WRITE TO MODULE
;6-ENABLE LINE = RE2 DATA FROM MICRO TO MODULE IS TRANSFERRED FROM HIGH TO LOW OF THE ENABLE SIGNAL
; DATA READ FROM MODULE TO MICRO IS TRANSFERRD FROM LOW TO HI OF THE ENABLE SIGNAL
;7-DATA BIT 0 = NC
;8-DATA BIT 1 = NC
;9-DATA BIT 2 = NC
;10-DATA BIT 3 = NC
;11-DATA BIT 4 = RD4
;12-DATA BIT 5 = RD5
;13-DATA BIT 6 = RD6
;14-DATA BIT 7 = RD7
;15-BACK LIGHT +VE --CAN BE CONNECTED TO ANY PIN
ORG 0000H
;GOTO MAIN
;HIGH PRIORITY INTERRUPT VECTOR
ORG 0008H
;LOW PRIORITY INTERRUPT VECTOR
ORG 0018H
ORG 0020H
; INITIAIZATION
;MAIN PROGRAM
ORG 0050H
;INITIALIZATION
MOVLW 0FH ; INITIALIZE ALL PORTS AS DIGITAL INPUTS
MOVWF ADCON1
MOVLW 07H ;CONFIGURE COMPARATORS FOR DIGITAL INPUTS
MOVWF CMCON
CLRF TRISE
CLRF PORTE
MOVLW B'00000000' ;PORTD IS CONFIGURED AS OUTPUTS AND INPUTS
MOVWF TRISD
CLRF LATD
CLRF PORTD
MAIN
MOVLW B'00110001' ;ASSUMING THIS IS THE ADC RESULT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
MOVWF REG1
CALL LONG_DELAY
CALL LONG_DELAY
FUNCTION_SET
BCF PORTE,0
BCF PORTE,1
movlw 38H
movwf PORTD
CALL PULSE_E
CALL SMALL_DELAY
CALL SMALL_DELAY ; I would initialise 0x33, 0x33, 0x38, 0xF, Ox1...
DISPLAY_ON
BCF PORTE,0
BCF PORTE,1
movlw 0FH
movwf PORTD
CALL PULSE_E
CALL SMALL_DELAY
CALL SMALL_DELAY
CLRF table
MESSAGE
MOVF table,W ; Increase message pointer
CALL TEXT
ANDLW 0FFH ; Check for NULL
BTFSC STATUS,Z
GOTO STOP ; Done
BSF PORTE,0
BCF PORTE,1
MOVWF PORTD ; Print
CALL PULSE_E
CALL SMALL_DELAY
CALL SMALL_DELAY
INCF table,F
GOTO MESSAGE
STOP
GOTO STOP
TEXT
MOVWF table_temp
BCF STATUS,C
RLCF table_temp,F
MOVLW HIGH(mess) ; Get High address
BTFSC STATUS, C ; If > 255
INCF WREG,W ;
MOVWF PCLATH
MOVLW LOW(mess) ; Get low address
ADDWF table_temp,W ; add message pointer
BTFSC STATUS,C ; if > 255
INCF PCLATH,F
MOVWF PCL
mess
RETLW REG1 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
RETLW 'E'
RETLW 'L'
RETLW 'L'
RETLW 'O'
RETLW 0H
PULSE_E
BSF PORTE,2
NOP
BCF PORTE,2
RETURN
LONG_DELAY
movlw D'2'
movwf COUNT1
movlw D'69'
movwf COUNT2
movlw D'169'
movwf COUNT3
loop
decfsz COUNT3
goto loop
decfsz COUNT2
goto loop
decfsz COUNT1
goto loop
RETURN
SMALL_DELAY
MOVLW .10
MOVWF COUNT2
LABEL2
CLRF COUNT1
LABEL1
DECFSZ COUNT1
GOTO LABEL1
DECFSZ COUNT2
GOTO LABEL2
RETURN
SEND
GOTO $
END
COUNT1 EQU 60H
COUNT2 EQU 61H
COUNT3 EQU 62H
TABLE_TEMP EQU 63H
TABLE EQU 64H
REG 1 EQU 65H ;<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
ORG 0000H
;INITIALIZATION
MOVLW 0FH ; INITIALIZE ALL PORTS AS DIGITAL INPUTS
MOVWF ADCON1
MOVLW 07H ;CONFIGURE COMPARATORS FOR DIGITAL INPUTS
MOVWF CMCON
CLRF TRISE
CLRF PORTE
MOVLW B'00000000' ;PORTD IS CONFIGURED AS OUTPUTS AND INPUTS
MOVWF TRISD
CLRF LATD
CLRF PORTD
MAIN
MOVLW B'00110001' ;<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
MOVWF REG1
CALL LONG_DELAY
FUNCTION_SET
BCF PORTE,0
BCF PORTE,1
MOVLW 38H
MOVWF PORTD
CALL PULSE_E
CALL SMALL_DELAY ; I would initialise 0x33, 0x33, 0x38, 0xF, Ox1...
DISPLAY_ON
BCF PORTE,0
BCF PORTE,1
MOVLW 0CH
MOVWF PORTD
CALL PULSE_E
CALL SMALL_DELAY
CLRF TABLE
MESSAGE
MOVF TABLE,W ; Increase message pointer
CALL TEXT
ANDLW 0FFH ; Check for NULL
BTFSC STATUS,Z
GOTO SEND_A2D_RESULT ;<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
BSF PORTE,0
BCF PORTE,1
MOVWF PORTD ; Print
CALL PULSE_E
CALL SMALL_DELAY
INCF TABLE,F
GOTO MESSAGE
TEXT
MOVWF TABLE_TEMP
BCF STATUS,C
RLCF TABLE_TEMP,F
MOVLW HIGH(mess) ; Get High address
BTFSC STATUS, C ; If > 255
INCF WREG,W ;
MOVWF PCLATH
MOVLW LOW(mess) ; Get low address
ADDWF TABLE_TEMP,W ; add message pointer
BTFSC STATUS,C ; if > 255
INCF PCLATH,F
MOVWF PCL
mess
RETLW 'I'
RETLW 't'
RETLW 's'
RETLW ' '
RETLW 'W'
RETLW 'o'
RETLW 'r'
RETLW 'k'
RETLW 'i'
RETLW 'n'
RETLW 'g'
RETLW ' '
RETLW 'X'
RETLW 'D'
RETLW 0H
SEND_A2D_RESULT ;<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
MOVFF REG1,PORTD
CALL PULSE_E
GOTO SEND
PULSE_E
BSF PORTE,2
NOP
BCF PORTE,2
RETURN
LONG_DELAY
MOVLW .2
MOVWF COUNT1
MOVLW .69
MOVWF COUNT2
MOVLW .169
MOVWF COUNT3
loop
DECFSZ COUNT3
GOTO loop
DECFSZ COUNT2
GOTO loop
DECFSZ COUNT1
GOTO loop
RETURN
SMALL_DELAY
MOVLW .10
MOVWF COUNT2
LABEL2
CLRF COUNT1
LABEL1
DECFSZ COUNT1
GOTO LABEL1
DECFSZ COUNT2
GOTO LABEL2
RETURN
SEND
GOTO $ ; THIS WILL STOP THE MICRO FROM STARTING TO EXECUTRE THE PROGRAME AGAIN EVEN AFTER
; SENDING IT TO THE END DIRECTIVE
END
; USE OF TABLES
; LCD DRIVER
; DETERMINING THE LOATION WHERE WE WANT THE WORDS TO START
; USING A LOOP TO DIREGARD THE FIRST 4 LTTERS AND START OUTPUTING FROM THE FIFTH LETTER
; WRITING IN LOWER ROW
; CONVERTING FROM 8 BIT TO 4 BIT
LIST P=18F4550, F=INHX32 ;directive to define processor
#include <P18F4550.INC> ;processor specific variable definitions
CONFIG FOSC = HSPLL_HS ; XT oscillator, PLL enabled, XT used by USB
; CONFIG PLLDIV = 5 ; No prescale (20 MHz oscillator divide by 5 drives PLL directly)
CONFIG PLLDIV = 1 ; No prescale (4 MHz oscillator)
CONFIG CPUDIV = OSC1_PLL2 ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
; PLL Prescaler Selection bits:
; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly)
; PLLDIV = 2 Divide by 2 (8 MHz oscillator input)
; PLLDIV = 3 Divide by 3 (12 MHz oscillator input)
; PLLDIV = 4 Divide by 4 (16 MHz oscillator input)
; PLLDIV = 5 Divide by 5 (20 MHz oscillator input)
; PLLDIV = 6 Divide by 6 (24 MHz oscillator input)
; PLLDIV = 10 Divide by 10 (40 MHz oscillator input)
; PLLDIV = 12 Divide by 12 (48 MHz oscillator input)
;
; CPU System Clock Postscaler:
; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
CONFIG USBDIV = 2 ; USB clock source comes from the 96 MHz PLL divided by 2
; CONFIG FCMEM = OFF ; Fail-Safe Clock Monitor disabled
CONFIG IESO = OFF ; Oscillator Switchover mode disabled
; CONFIG WDT = OFF ; HW Disabled - SW Controlled
;----- CONFIG2H Options --------------------------------------------------
CONFIG WDT = OFF ; HW Disabled - SW Controlled
; CONFIG WDT = ON ; HW Enabled - SW Disabled
;WDTPS_1_2H EQU H'E1' ; 1:1
;_WDTPS_2_2H EQU H'E3' ; 1:2
;_WDTPS_4_2H EQU H'E5' ; 1:4
;_WDTPS_8_2H EQU H'E7' ; 1:8
;_WDTPS_16_2H EQU H'E9' ; 1:16
;_WDTPS_32_2H EQU H'EB' ; 1:32
;_WDTPS_64_2H EQU H'ED' ; 1:64
;_WDTPS_128_2H EQU H'EF' ; 1:128
;_WDTPS_256_2H EQU H'F1' ; 1:256
;_WDTPS_512_2H EQU H'F3' ; 1:512
;_WDTPS_1024_2H EQU H'F5' ; 1:1024
;_WDTPS_2048_2H EQU H'F7' ; 1:2048
;_WDTPS_4096_2H EQU H'F9' ; 1:4096
;_WDTPS_8192_2H EQU H'FB' ; 1:8192
;_WDTPS_16384_2H EQU H'FD' ; 1:16384
CONFIG WDTPS = 32768 ; 1:32768
CONFIG PWRT = OFF ; PWRT DISabled
;CONFIG BOR = OFF ; Brown-out Reset disabled in hardware and software
;CONFIG BOR = SOFT ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
;CONFIG BOR = ON_ACTIVE ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
;CONFIG BOR = ON ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
;CONFIG BORV = 0 ; Maximum setting
;CONFIG BORV = 1 ;
;CONFIG BORV = 2 ;
CONFIG BORV = 3 ; Minimum setting
;CONFIG VREGEN = OFF ; USB voltage regulator disabled
CONFIG VREGEN = ON ; USB voltage regulator enabled
CONFIG MCLRE = ON ; MCLR pin enabled; RE3 input pin disabled
CONFIG LPT1OSC = OFF ; Timer1 configured for higher power operation
;CONFIG LPT1OSC = ON ; Timer1 configured for low-power operation
CONFIG PBADEN = OFF ; PORTB<4:0> pins are configured as digital I/O on Reset
;CONFIG PBADEN = ON ; PORTB<4:0> pins are configured as analog input channels on Reset
CONFIG CCP2MX = OFF ; CCP2 input/output is multiplexed with RB3
; CONFIG CCP2MX = ON ; CCP2 input/output is multiplexed with RC1CCP2MX = OFF
; CONFIG STVREN = OFF ; Stack full/underflow will not cause Reset
CONFIG STVREN = ON ; Stack full/underflow will cause Reset
CONFIG LVP = OFF ; Single-Supply ICSP disabled
; CONFIG LVP = ON ; Single-Supply ICSP enabled
CONFIG ICPRT = OFF ; ICPORT disabled
; CONFIG ICPRT = ON ; ICPORT enabled
CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
; CONFIG XINST = ON ; Instruction set extension and Indexed Addressing mode enabled
; CONFIG DEBUG = ON ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
CONFIG DEBUG = OFF ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
;CONFIG CP0 = ON ; Block 0 (000800-001FFFh) code-protected
CONFIG CP0 = OFF ; Block 0 (000800-001FFFh) not code-protected
; CONFIG CP1 = ON ; Block 1 (002000-003FFFh) code-protected
CONFIG CP1 = OFF ; Block 1 (002000-003FFFh) not code-protected
; CONFIG CP2 = ON ; Block 2 (004000-005FFFh) code-protected
CONFIG CP2 = OFF ; Block 2 (004000-005FFFh) not code-protected
;----- CONFIG5H Options --------------------------------------------------
; CONFIG CPB = ON ; Boot block (000000-0007FFh) code-protected
CONFIG CPB = OFF ; Boot block (000000-0007FFh) not code-protected
; CONFIG CPD = ON ; Data EEPROM code-protected
CONFIG CPD = OFF ; Data EEPROM not code-protected
;----- CONFIG6L Options --------------------------------------------------
;CONFIG WRT0 = ON ; Block 0 (000800-001FFFh) write-protected
CONFIG WRT0 = OFF ; Block 0 (000800-001FFFh) not write-protected
; CONFIG WRT1 = ON ; Block 1 (002000-003FFFh) write-protected
CONFIG WRT1 = OFF ; Block 1 (002000-003FFFh) not write-protected
; CONFIG WRT2 = ON ; Block 2 (004000-005FFFh) write-protected
CONFIG WRT2 = OFF ; Block 2 (004000-005FFFh) not write-protected
;----- CONFIG6H Options --------------------------------------------------
CONFIG WRTB = ON ; Configuration registers (300000-3000FFh) write-protected
;CONFIG WRTB = OFF ; Configuration registers (300000-3000FFh) not write-protected
;CONFIG WRTC = ON ; Boot block (000000-0007FFh) write-protected
CONFIG WRTC = OFF ; Boot block (000000-0007FFh) not write-protected
;CONFIG WRTD = ON ; Data EEPROM write-protected
CONFIG WRTD = OFF ; Data EEPROM not write-protected
;----- CONFIG7L Options --------------------------------------------------
;CONFIG EBTR0 = ON ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks
CONFIG EBTR0 = OFF ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
;CONFIG EBTR1 = ON ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks
CONFIG EBTR1 = OFF ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
;CONFIG EBTR2 = ON ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks
CONFIG EBTR2 = OFF ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
;----- CONFIG7H Options --------------------------------------------------
;CONFIG EBTRB = ON ; Boot block (000000-0007FFh) protected from table reads executed in other blocks
CONFIG EBTRB = OFF ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks
; PRIMARY CLOCK IS A 4MHZ CRYSTAL CONNECTED TO PINS 13/14
; PRESCALING TO 48MHZ CORE SPEED AND 48MHZ USB ENGINE SPEED
; DECLERATIONS MUST BE PLACED IN LOWER HALF OF ACCESS BANK (160 GPRs) BECAUSE THE HIGHER
; HALF OF ACCESS BANK IS COMPOSED OF SFRs. RANGE OF LOWER HALF IS FROM 60H - FFH.
OD EQU 60H
OE EQU 61H
OF EQU 62H
O5 EQU 65H
O6 EQU 63H
COUNT1 EQU 66H
COUNT2 EQU 64H
COUNT3 EQU 67H
table_temp EQU 68H
table EQU 69H
REG1 EQU 6AH
ONES EQU 6BH
TENS EQU 6CH
HUND EQU 6DH
NUMBL EQU 6EH
NUMBH EQU 6FH
TMP EQU 70H
; LCD DISPLAY PINOUTS
; 1-GROUND, 2-VDD,
; 3- VO(CONTRAST CONTROL)CONNECTED TO GROUND
; 4-REGISTER SELECT = RE0 LOGIC 1 IF MICRO IS TRANSFERRING DATA
; LOGIC 0 IF MICRO IS TRANSFERRING A COMMAND
; 5-READ/WRITE = RE1 LOGIC 1 TO READ FROM MODULE
; LOGIC 0 TO WRITE TO MODULE
; 6-ENABLE LINE = RE2 DATA FROM MICRO TO MODULE IS TRANSFERRED FROM HIGH TO LOW OF THE ENABLE SIGNAL
; DATA READ FROM MODULE TO MICRO IS TRANSFERRD FROM LOW TO HI OF THE ENABLE SIGNAL
; 7-DATA BIT 0 = NC
; 8-DATA BIT 1 = NC
; 9-DATA BIT 2 = NC
; 10-DATA BIT 3 = NC
; 11-DATA BIT 4 = RD4
; 12-DATA BIT 5 = RD5
; 13-DATA BIT 6 = RD6
; 14-DATA BIT 7 = RD7
; 15-BACK LIGHT +VE --CAN BE CONNECTED TO ANY PIN
ORG 0000H
; GOTO MAIN
;HIGH PRIORITY INTERRUPT VECTOR
ORG 0008H
;LOW PRIORITY INTERRUPT VECTOR
ORG 0018H
ORG 0020H
;INITIAIZATION
;MAIN PROGRAM
ORG 0050H
;INITIALIZATION
MOVLW 0FH ; INITIALIZE ALL PORTS AS DIGITAL INPUTS
MOVWF ADCON1
MOVLW 07H ;CONFIGURE COMPARATORS FOR DIGITAL INPUTS
MOVWF CMCON
CLRF TRISE
CLRF PORTE
MOVLW B'00000000' ;PORTD IS CONFIGURED AS OUTPUTS AND INPUTS
MOVWF TRISD
CLRF LATD
CLRF PORTD
MAIN
CALL LONG_DELAY
CALL LONG_DELAY
MOVLW .154 ; Could be adc input
MOVWF REG1
;INIT DISPLAY
movlw 33H
CALL LCDCOMMAND
CALL LONG_DELAY
movlw 38H
CALL LCDCOMMAND
CALL SMALL_DELAY
movlw 0FH
CALL LCDCOMMAND
CALL SMALL_DELAY
movlw 01H
CALL LCDCOMMAND
CALL SMALL_DELAY ; I would initialise 0x33, 0x33, 0x38, 0xF, Ox1...
CLRF table
MESSAGE
MOVF table,W ; Increase message pointer
CALL TEXT
ANDLW 0FFH ; Check for NULL
BTFSC STATUS,Z
GOTO MESSFIN ; Done
CALL LCDDATA
INCF table,F
GOTO MESSAGE
MESSFIN
MOVF REG1,W
MOVWF NUMBL
CALL BIN2BCD
MOVF TENS,W
ANDLW 0FH
ADDLW 30H
CALL LCDDATA
CALL SMALL_DELAY
SWAPF ONES,W
ANDLW 0FH
ADDLW 30H
CALL LCDDATA
CALL SMALL_DELAY
MOVF ONES,W
ANDLW 0FH
ADDLW 30H
CALL LCDDATA
CALL SMALL_DELAY
STOP
GOTO STOP
LCDDATA
BSF PORTE,0
BCF PORTE,1
movwf PORTD
CALL PULSE_E
CALL SMALL_DELAY
CALL SMALL_DELAY
RETURN
LCDCOMMAND
BCF PORTE,0
BCF PORTE,1
movwf PORTD
CALL PULSE_E
CALL SMALL_DELAY
CALL SMALL_DELAY
RETURN
TEXT
MOVWF table_temp
BCF STATUS,C
RLCF table_temp,F
MOVLW HIGH(message) ; Get High address
BTFSC STATUS, C ; If > 255
INCF WREG,W ;
MOVWF PCLATH
MOVLW LOW(message) ; Get low address
ADDWF table_temp,W ; add message pointer
BTFSC STATUS,C ; if > 255
INCF PCLATH,F
MOVWF PCL
message
RETLW 'V'
RETLW 'A'
RETLW 'L'
RETLW 'U'
RETLW 'E'
RETLW ' '
RETLW '='
RETLW ' '
RETLW 0H
PULSE_E
BSF PORTE,2
NOP
BCF PORTE,2
RETURN
BIN2BCD
MOVLW D'5'
MOVWF COUNT1
CLRF ONES
CLRF TENS
RLCF NUMBL,F
RLCF ONES,F
RLCF NUMBL,F
RLCF ONES,F
RLCF NUMBL,F
RLCF ONES,F
REPEAT
MOVF ONES,W
ADDLW 0x33
MOVWF TMP
MOVF ONES,W
BTFSC TMP,3
ADDLW 0x03
BTFSC TMP,7
ADDLW 0x30
MOVWF ONES
RLCF NUMBL,F
RLCF ONES,F
RLCF TENS,F
DECFSZ COUNT1,F
GOTO REPEAT
RETURN
LONG_DELAY
movlw D'2'
movwf COUNT1
movlw D'69'
movwf COUNT2
movlw D'169'
movwf COUNT3
loop
decfsz COUNT3
goto loop
decfsz COUNT2
goto loop
decfsz COUNT1
goto loop
RETURN
SMALL_DELAY
MOVLW .10
MOVWF COUNT2
LABEL2
CLRF COUNT1
LABEL1
DECFSZ COUNT1
GOTO LABEL1
DECFSZ COUNT2
GOTO LABEL2
RETURN
SEND
GOTO $ ; THIS WILL STOP THE MICRO FROM STARTING TO EXECUTRE THE PROGRAME AGAIN EVEN AFTER
; SENDING IT TO THE END DIRECTIVE
END
Main program
....
...
...
call lcd_home_page
...
...
...
lcd_home_page
display: Home characters
return
Main program
....
...
...
display: Home characters
...
...
...
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