So I'm doing pipelined datapaths and i'm finding it very hard to understand.I'm familiar with single and multiple clock cycle datapaths but pipelined is proving to be a problem.
I've attached a picture of the datapath,I dont understand how they got the values 104 and 108 in the ID/EX stage.Also the 105 in the EX/MEM stage as well as the 210 in the MEM/WB stage.
All registers initially have 100 stored in them.Anyone care to explain this?the whole forwading thing is pretty confusing as well,
![datapath.png datapath.png](https://www.electro-tech-online.com/data/attachments/55/55020-22b0d5e647adf29edeaf3b6a20c13cb5.jpg)
![datapath.png datapath.png](https://www.electro-tech-online.com/data/attachments/55/55020-22b0d5e647adf29edeaf3b6a20c13cb5.jpg)
I've attached a picture of the datapath,I dont understand how they got the values 104 and 108 in the ID/EX stage.Also the 105 in the EX/MEM stage as well as the 210 in the MEM/WB stage.
All registers initially have 100 stored in them.Anyone care to explain this?the whole forwading thing is pretty confusing as well,
![datapath.png datapath.png](https://www.electro-tech-online.com/data/attachments/55/55020-22b0d5e647adf29edeaf3b6a20c13cb5.jpg)
![datapath.png datapath.png](https://www.electro-tech-online.com/data/attachments/55/55020-22b0d5e647adf29edeaf3b6a20c13cb5.jpg)