PLD-Programming

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Boncuk

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Hi everbody,

I have downlaoded a project off a japanese site which involves a PLD (Lattice ispLSI2032/E).

Looking at Lattice Semiconductors I can't find any information concerning programming of that device.

The ISP-connector is an 8-pin box header with 7 pins connected to the PLD.

The signal nets are not labelled in the schematic and I have no idea which signals are used for programming.

Anybody there having experience with PLDs?

Regards

Hans
 
https://www.electro-tech-online.com/custompdfs/2008/05/lattice_cable.pdf
**broken link removed**
http://elm-chan.org/works/avrx/lattice.png
**broken link removed**

I've used the top one, only tested on MACH4A5 (about 6 years ago lol).

You will also need 'ispVM' download software. For which lattice will probably ask you to get a license, but you may be able to request it, just say you're student. As for the whole software, they do a trial version for a few select CPLD's/FPGA's for 6 months. Or possibly for free if its the 'Classic' version, which only supports the older chips like yours.

Lattice are very shadey about their hardware/software, which is why I switched to Xilinx and Altera. Also the LSI2032 is pretty old, I'm not sure its widely available (mature product).

Regards,

Blueteeth
 
I have experience with PLDs, but not with Lattice, only with Xilinx. Xilinx CPLDs are programmed using JTAG and it is quite easy with PC parallel port. I have seen even Xilinx CPLD JTAG connections directly hooked to the parallel port.
Xilinx itself supports this but they use 74HC125 as a buffer to separate the PLD from the parallel port (Xilinx Parallel cable III). Also Xilinx software (ISE Webpack) is free download.
 
PLD programming

Hi Blueteeth and petrv,

thank you very much for you reply. Programming via the parallel port is one more problem, since newer mainboards simply don't have it anymore, and so is mine. I already downloaded the buffered 25-Pin parallel port adapter and this is not very clear. The schematic differs a lot from the data sheet of the 74HC244, and of course, there are no pin numbers in the schematic.

To petrv,

since you have experience programming PLDs I would like to know if you could program one for me. I'll try to find an equivalent at Xilinx, send that and the programming code to you. All expenses will be on me.

Kind regards

Hans
 
Hi,

My motherboard also does not have a parallel port but - why don't you buy a PCI parallel port card ? It is not that expensive. (just no USB adapter, it will not work). You need a true hardware compatible parallel port.

The Xilinx parallel cable uses 74HC125, not 74HC244. Look for example here:

**broken link removed**

As for the PLD design - do you have the source (VHDL, Verilog) .... ?

Petr
 
Just out of interest, what would this project be? As in, what funciton would the CPLD play?

I ask because, looking at the 2032, its just a 32 MC device, and looks to be similar the MACH4A series, also has different timing specs.
Also, farnell DO stock it: https://uk.farnell.com/3327711/semi...sku=lattice-semiconductor-isplsi2032e-110lj44

Of course, Xilinx do very similar devices, as the 32-34 MC is the low end of the CPLD range. Handy little buggeres too.

And do you have the HDL language? or the *,jed* (jedec) file which can be downloaded into the device. The first would require 'fitting' with software (similar to compiling microcontroller code), where-as the JED is like a HEX file, and only requires the download software and parallel port adapter.

If you have access to a parallel port I can reverse-engineer my programming adapter. Just tested it, works like a charm.

Blueteeth
 
You won't find pin-compatible part but the Xilinx part will probably fit with a very small redesign. If I read the Lattice DS correctly it is a 32-register PLD
so you can try Xilinx XC9536 or XC9572 - both are in PLCC-44 package and pin compatible with each-other. XC9536XL or XC9572XL would be much cheaper but they require 3.3V power (but I/O is 5V tolerant) so if you have there a 3.3V power better use the cheaper 3.3V part (or add a LDO like LD1117-33 and use it anyway).
 
Blueteeth said:
Just out of interest, what would this project be? As in, what funciton would the CPLD play?
Click to expand...

It's a 2.4GHz eight digit (LED-display) frequency counter with both, analog and digital inputs. A prescaler divides the high frequencies by 64 and the PLD is used as a general prescaler and to switch functions as time base and frequency and 1/f. There are only few pins occupied on the PLD device. The design is interesting from the point, that most frequency counters have an error of one digit because they don't use signal synchronization, e.g. measuring mains frequency they would display 51Hz instead of 50.

I have never worked with PLDs and therefor I need all the help I can get. The design is very interesting because of parts which are normally not used in digital circuits, e.g. single HC-AND-gate in a SOT23-5 package, saving 7 pins and lots of space.

If you are interested in the article I'll send you all the information via email, including a first layout. The author never made a printed board. He was satisfied with wires.

Regards

Hans
 

Hi petrv,

I found an XC9536-5PC44C, 5 volt PLCC44 package. I guess this would match the Lattice device (32 registers). Having downloaded the data sheet there was no information about the pin layout of it. Where can I find that? (Very strange for a data sheet not containing a pin describtion.) The MCU beeing partly controlled by the PLD is an ATMEL AT90S8515-8J (also PLCC44).

Kind regards

Hans
 
Yeah Xilinx are also a bit weird (seems all the CPLD manufacturers haven't got the hang of a nice easy to read datasheet). In the datasheet for the XC9536** they do have pin mapping, but its not as easy to read as a nice diagram. Try these:

http://www.geocities.com/leon_heller/xc9536_sch.gif
**broken link removed**

And if you're using the PLCC package with a socket for through-hole prototyping:

**broken link removed**

Hope that helps.

Blueteeth
 
PLD programming

Hi Blueteeth,

according to the little information I had until now about JTAG and Power pins the schematic you suggested is obviously the one of a PLCC44 package.

Strange enough, many manufacturers shift the pin numbers by six between PLCC and VQ packages. E.g. TDI is at pin9 of a VQ44 package and it is at pin15 of a PLCC44 package.

Thank you very much for the info. I guess the XC9536-5PC44C is just the right replacement for the Lattice ispLSI2032E. It only takes some comparison to get the proper pins.

One more question just in case I can't get the device programmed. I have an English friend (Chris Shakespeare) who comes here every once in a while to visit his girl. If lives not to far from your home he could pick up the programmed device for me and pay what you charge for your work.

Is it OK for you if I talk to him in this matter?

Kind regards

Hans
 
I don't think it is practical to ask someone else to program the device (especially in another country) - especially in this case as you are going to do a little redesign - replacing the PLD - so you will need to have a new programming file. Obviously you cannot program Xilinx device with a file for Lattice device. If you have the sources (VHDL, Verilog ....) you can just run the synthesis tool and hope it will work, otherwise unfortunately you'll have to design the logic from the scratch. For each development there at least a few iterations and it would be extremely inpractical to ship the device to another country and back to reprogram it with the new version (after fixing a problem etc).

I assume you don't want to buy the Xilinx USB JTAG adapter ($160) so you can build the simple parallel port adapter with 74HC125 but you will need to buy a PCI parallel port card for your PC if you don't have a parallel port.
The card should not be that expensive (but as I said it must be PCI, not USB)
 

Wow! That's a lot of money for an item I will probably use once. The STK500 (ATMEL) is just 79.70 EURO and blueroomelectronics' Junebug (PICs) is US$ 49.00 (or close to that)

I made the parallel cable adapter already as a board design and a PCI parallel port card will cost 15.00 EURO. The adapter is pretty small considering that all parts are discretes including two 10pin box headers (2.4X2.1inch)

The programming, I guess, must be done anyway. All I have is a list of variables and in/out advices in word.doc format.

Regards

Hans
 
Last edited:
Ok so if you have the PCI parallel port card and built the adapter - not all parts are discretes, 74HC125 is IC not a discrete component. You *must* build the JTAG adapter exactly as specified by Xilinx otherwise it will not be compatible with their software.

So now the next step would be to get the free Xilinx ISE Webpack software. I hope you have a good internet connection, it is a very big download. Just register at www.xilinx.com (free, you just need a working e-mail address) and then download the ISE Webpack for free.

Then you can write the design, build the programming file and program the CPLD using your adapter. I can assure you will use the programming adapter more than one as Mr. Murphy says any design (non-trivial) contains at least one bug ...

Petr
 
I'd be happy to program a chip for you, be it lattice or Xilinx, but as petrv pointed out, simple PCI parallel port card + the parts for download cable (either a lattice OR a xilinx one) would just be less hassle for all concerned (especially your friend if he lives miles away from me ^^ ).

A few caveats for the download cable construction:
1) If your CPLD (again, xilinx or Lattice) is a 5v device, then thats fine, any form of TTL buffer would do. But if its a 3.3v device, many CPLD's require ISP downloading at their native VCC. Then agian, almost ALL 3.3v CPLD's are 5v tolerant, so you would just have to make sure you have a 3.3v power supply. As I said, if its 5v don't worry about it.

2) Some download cables connect two parallel port lines together as sort of loopback so the software recognises thats its plugged in...whether a device is connected to it or not. Don't forget it (my one cost me 5 hours of debugging).

Lets us know how you get on. And if you're looking for CPLD's, try ebay..I've recently just bought up about 30 different types, along with FPGA's, very cheap. total must be <100USD. Also...some even come with the dlownload cable pre-built still at ridiculous prices.

Blueteeth
 
PLD programming

Hi Blueteeth,

making a parallel cable should not be a problem. I suppose the loop backs are pins 8,11 and 12 for the Xilinx devices and pins 8,12 and 13 for the Lattice devices. (Pin numbers of the Sub-D25 male connector) The Lattice cable is not clear at all. It uses a 74HC244 and the logical symbols differ a lot from those in the data sheet. Additionally there are no pin numbers of the IC (HC244) contained in the schematic.

Is it correct to use only pins 20 and 25 of the Sub-25 connector for ground? Normally they are 18 through 25.

What worries me most is the fact, that there are pin describtions of the JTAG and power pins in the data sheet of the XC9536, but none for the I/O numbers. The programming software certainly doesn't know what is connected to which pin in the application. How did you find out the pin numbers and the I/O associated with them? (Try and fry? )

I guess, Chris needs a weekend trip from time to time. I'm not worried about that if I need his help.

If you happen to have a better schematic of the Lattice Port Adapter please foreward that to me.

Thank you very much for your help.

Regards

Hans
 
The Xilinx adapter is powered from the target circuit so it always outputs correct voltage levels on the JTAG pins, be it 5V or 3.3V - the 74HC125 can accept any voltage in the range 2V to 6V as power (Vcc). The Xilinx XC95..XL 3.3V family has 5V tolerant I/O and the devices are cheaper than th 5V XC95... family (but you will need a 3.3V regulator to power the CPLD).

I/O pin assignment - this is done when building the programming file using an .ucf file (User Constraint file). If you don't specify this file it will use whatever pins are the most convenient when the ISE Webpack creates the implementation but if you have designed the PCB with specific I/O pins going to be used for specific pins of your design, you must use the .ucf file to give location constraints. For example you can specify that input pin DATA1 of your design goes to pin 33 of your physical CPLD package.
 
Last edited:
PLD programming

Hi petrv,

thank you for the information. However it is getting confusing more and more.

I attached a fraction of the schematic with all pins labelled. The output pins of the AT90S8515 are all used for the 8-digit LED display.

If you have the time would you kindly make a "translation" from Lattice to Xilinx pin numbers?

Regards

Hans
 
Last edited:
Hi,

do you have the understanding of the function the PLD is supposed to perform ?
This is essential for you to succeed, otherwise you can't do it, the same as you cannot for example replace a microcontroller in a design with a different type (e.g PIC with AVR or the other way) if you have no idea what is the software inside doing ... same with the PLD. Could you define the function - e.g. as a schematic using TTL logic ? Or a good description what it does ?
If yes then it is the time to start the Webpack (I hope you downloaded and installed it already) and start the new design wizard ... The I/O pin assignment is just a small thing but you need first to design the logic that goes into that CPLD.

Petr
 
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