PLD-Programming

[Blueteeth]

Hi petrv,

thank you for the information. However it is getting confusing more and more.

I attached a fraction of the schematic with all pins labelled. The output pins of the AT90S8515 are all used for the 8-digit LED display.

If you have the time would you kindly make a "translation" from Lattice to Xilinx pin numbers?

Regards

Hans

As petrv mentioned....the pins a cpld use is entirely down to the user. If you have a design that uses only 5 I/O's....then you can use any I/O for any of them (except obviously the JTAG and power/gnd pins). This is indeed 'confusing' if you don't have the source code. As a jeduc/hex file for the CPLD will already have this information. In which case you'll have to use the original device and it can then be used exactly as in the schematic (its I/O's are already assigned).

A translation from lattice to xilinx part numbers is sort of down to you This is why sometimes it isn't best to change horses.

If you have the VHDL/verilog/schematic source, then as petrv suggested, xilinx ISE webpack will happily take this, then you map the I/O's (in the design each input/output wil have a name, just tell the software what names go to what pins). Set the device, and program. I will pm you my email address, and if you want, email me the source/url or the project.


Right now I see we've got several problems that need to be solved:

1. Decide whether you can get the lattice CPLD in question (2032), or whether it is easier for you to aquire a xilinx equivilent (part numbers already mentioned).

2. IF you have the code/schematic (for programming the CPLD) then you can use either lattice OR xilinx parts. If you only have tghe jedec file, you're pretty much stuck with having to use the Lattice 2032.

2a. As another option (not an easy one). If you know exactly what the CPLD is supposed to do, then I suppose I could attempt to write some VHDL or create a CPLD schematic and send it to you, so you can use it for XIlinx OR Lattice parts.

3. Download cable. As you seem happy to get a PCI parallel port card, then its just a case of getting decent schematics for the cable. Again, xilinx or Lattice? Xilinx have some easy-to-read schems, but as you rightly pointed out, the schem for the lattice cable is a bit of bugger. I shall reverse engineer my DIY download cable (works with every lattice part I got) and provide a Eagle schem, parts list, and if you REALLY want, a stripboard layout. Or even if you are willing to make a PCB for it (works jsut fine on stripboard) I may even be nice enough to design a custom PCB

So, there are all the options. It is indeed confusing, took me ages to get the hang of using CPLD's but once you get it, its pretty cool, and extremely handy.

As I said, I shall send you a personal message in this board with my email address. Send me all the info you have on the project. If its on a webpage, then a url would be fine...if you have source codes, send them. Obviously I won't really need the microcontroller code, its all about that Lattice thing.

Good luck, we'll get there eventually mate.

Blueteeth

 

[petrv]

Hi,
in addition to my previous post, you can read my tutorial on programming CPLDs.

Regarding the schematics you have posted - I need to see the complete schematics, this part is too small to understand it enough. If all that you need is a prescaler it should not be that hard to implement in VHDL but I still don't have enough information about the project to give you more specific advice.

 

[Boncuk]

PLD programming

Hi petrv,

I know that I can use any pin of a CPLD for I/O, except for the reserved (programming) pins.

The file I already mentioned (word document) seems to be a UC file. There are exact pin describtions and functions contained in it.

Sorry, I couldn't download any software until now. First, Thailand has a big problems concerning internet band width. A file of more than 600MB size takes about 24 hours to download. Second, even if I start download the electric power supply will fail for sure within those 24 hours. Using a UPS (which I do) won't make much difference if the power failure lasts more than 30 minutes.

I also read your tutorial. For this time I think it will be better to stick with Lattice.

I sent the complete schematic and every information to it already to blueteeth. If you are interested you might take a look at the file and find out if it is good enough to program the chip.

Thanks to both of you for your kindness and patience with a man who starts grasping things slower.

Regards

Hans


Sorry, upload won't work. Friday evening - Thailand is playing.

 

[Blueteeth]

Hi petrv,

Sorry, I couldn't download any software until now. First, Thailand has a big problems concerning internet band width. A file of more than 600MB size takes about 24 hours to download....

Yeah, the software for CPLD's/FPGAs, be it lattice or xilinx is ridiculous. 400-700MB. Shocker.

Thanks to both of you for your kindness and patience with a man who starts grasping things slower.

You're welcome. I had a slow start to programmable logic, I guess its complicated because of the nature of CPLD's (completely reconfigurable in every way) but we'll get there.

And to petrv, good too see someone else is up on PLD's, you've proved invaluable in this thread, and to this forum. Keep it up

Blueteeth.

No rush on the files, whenever your internet decides to work. Annoying isn't it?

 

[Boncuk]

Yeah, the software for CPLD's/FPGAs, be it lattice or xilinx is ridiculous. 400-700MB. Shocker.

It's not only Lattice and Xilinx. Look at ATMEL's AVR-Studio. It's about the same. Programmers tend to become sloppy knowing there is a lot of memory to work with, other than working with 61KB of RAM space using C/PM some time ago.

The problem in Thailand is selfmade. Thailand supplies every neighbor country, Cambodia, Laos, Birma (Myanmar) and Malaysia with internet service, including the servers. Those countries don't have own internet servers. Using steam driven servers they won't do much of band width.

I tried internet via an analog modem before. The amazing download speed was 50bits/second.

Hans

 

[blueroomelectronics]

I had to repair my notebook recently, the power connector came loose from stress. Anyway I pulled the analog modem out while I had it apart. Never used the thing and all it did was chew away at the batteries and as it was a software modem it was just one less driver to worry about.

 

[Boncuk]

PLD programming

Hi petrv,

I hope the upload will work this time.

 

[petrv]

So where is your upload ? BTW regarding the Xilinx Webpack download they do have a download manager so you can resume interrupted downloads if there was a problem with your internet connection. Still I guess I am lucky having access to 5-Mbit ADSL connection I have just upgraded the Webpack from 9.1 to 10.1 and the download size has doubled (was over 1 GB now over 2 GB) And then also the service pack and IP upgrade pack ...
But all downloaded and installed it works very well.

Another possibility is to order the webpack installation DVD for a small fee from Xilinx.
I have got a DVD with the ISE Webpack when I bought the Spartan 3E starter kit from Xilinx 2 years ago ... (one of my 3 FPGA boards, other two are from XESS homepage announcements)

FPGAs programmed in almost the same way as CPLDs but they are much more powerful.
For example I have implemented the ZX Spectrum 48k 8-bit computer as a SoC all inside one FPGA ...

When you start using PLDs and especially FPGAs you'll discover how much hey are powerful.

Petr

 

[Boncuk]

So where is your upload ? Petr

I would certainly like to upload a file. According to Nigel Goodwin's information there was an aparent upgrade of the software at electro-tech-online. I tend to believe it was a downgrade - no possibity for attachments.

Good you have high speed. That's what Thais are dreaming of - me too.

Hans

Correction: Now the option is here again - done

 

[Blueteeth]

Hey,

I replied to your email, and sent my own lattice cable schem. But I got an automated response, so I sent it again ^^

And thinking about it, I have a few MACH4A5-32/32 's here, lattice, 32MC, pretty quick, similar pinout, same package (PLCC). If you like I could put that CPLD design into my software, load it into the chip, and send it. Just tell me what pins you would like each function to be.
Blueteeth

 

[Boncuk]

PLD programming

Hi Blueteeth,

thank you very much for your kind offer. Let me download the data sheet of the MACH4. It is no problem to purchase a single device in Germany. It costs EURO 5.80 incl. sales tax. The minimum order there is EURO 10.00. No problem at all. Might be interesting for you too. 24 hour delivery service at lowest possible shipment cost: Reichelt Elektronik - OnlineShop für PC-Komponenten, Elektronik - Festplatten, Mainboards, Motherboards, Karten, Kabel.

If you habe problems ordering there I would be happy to help you. I've been working with Reichelt for more than 40 years and their service is perfect - much better than Conrad.

In that matter you might as well forget about Thailand. You can buy all kinds of industrial overproduction parts and all kind of junk here, but never a specific part.

I received your email OK. I guess OAL just sends you a reply that the mail has landed.

Greetings

Hans

 

[petrv]

Hi Hans,
the code for the PLD is in ABEL. Unfortunately I don't use ABEL, only VHDL - actually this is the first ABEL code I have seen. I have checked the Xilinx tutorial on ABEL and according to that I got some understanding of the code (It seems to me that ABEL is much more primitive and low-level language than VHDL). I rewrote (yesterday) the logic in VHDL and ran synthesis for XC9536 - was ok with about 53% usage of the CPLD resources and I have got a programming file.

It is not the best design (one of the rules of a good PLD design is to run all flip flops from a single clock and "gated" clocks are not a good idea) but it should work for your application.

 

[Boncuk]

PLD programming

Hi petrv,

I don't know exactly what the "gated" clock is good for, but I imagine the clock frequency of 12.8MHz is divided by some factor to match the ATMEL CPUs requirements. The clock signal for the CPLD is supplied directly by a XTAL-oscillator circuit.

I also don't know about ABEL or VHDL. I just want to build that frequency counter, of which I think it's worth building it, just because using the proper prescaler it is able to work up to 2.4GHz with an eight-digit display

It's also a matter of calculation. A frequency counter off the shelf with these properties will cost me about 300 EURO. The few parts required to build it will not cost more than 100 EURO. And after all - it's self made which I like.

Thank you so much your work. May be I try to build two samples, one using a Lattice device and the other one with a Xilinx CPLD.

Hans

 

[petrv]

Hi Hans,

Gated clock and its problems:

I assume you are familiar with TTL logic ICs like 7408,7474,7493,74161 ... (no matter what technology - LS, HC, HCT, AC, LVC ...)

Suppose you have a D flip-flop (like one half of 7474) and you need to update the output at the rising edge of a system clock but only when a certain condition (e.g. signal COND is true).

Normally the D flip flop will copy the logic level at its input D to its output Q at each rising edge of the clock CLK. One idea how to implement the condition is to add a combinatorial logic like for example an AND gate (7408) with inputs connected to the clock CLK and the condition signal COND. the output will go to the CLK pin of the D flip-flop. This is what is called a "gated clock" and it is not a very good design for several reasons. A good design is to connect all CLK input to all flip-flop and connect them to the same global clock signal (programmable logic devices are specifically optimized for such kind of design).

Of course if you connect the CLK without the gate the flip-flop will be updated every rising edge (unconditionally) but you can still implement the required functionality in another way - add a multiplexor (like 1/4 of 74157) to the D input of the flip-flop
and connect one input (A) of the MUX to the signal that was connected to the D gate and the other input (B) to the output Q of the flip flop. the condition will go to the mux switch (A/B). That means the condition will select which input of the MUX will be loaded into the flip flop. if it is the (A) input the FF will be updated normally,
if it is the (B) the D of the FF is connected in effect to Q so it is updated with its previous value which will seem like no update.

This is for example the difference between asynchronous (ripple) counters like 7493 and synchronous like 74161 or 74193. The synchronous counter has all CLK inputs of all its flip-flops connected together so all outputs are updated synchronously. But with asynchronous design some flip-flops are updated later as the clock is delayed and there are moments when some of the outputs are already updated and others not yet.

Luckily for you your CPLD design will run only on a low 12.8 MHz clock so these problem will not be significant but the Xilinx CPLD can run on clock higher than 100 MHz (the 3.3V XL family is even faster) and then this issues can be a real problem.

Petr

the other

 

[Hero999]

I assume you are familiar with TTL logic ICs like 7408,7474,7493,74161 ... (no matter what technology - LS, HC, HCT, AC, LVC ...)

I know that you probably know this and I hate to be picky but half of those technologies aren't actually TTL but CMOS.

 

[petrv]

Of course I know that but in this case it is a completely irrelevant detail. As I said the technology (be it LSTTL or advanced CMOS) is not important for understanding the principle of synchronous design, on the contrary, too many not relevant details can distract from the subject

Petr

 

[Blueteeth]

I've skimmed over the abel file (my native HDL language) and it looks fine to me.
Yes, maybe some bad practice with the 'gated clocks', but that only serves to limit its maximum operating frequency. So unless the user is planning to run the thing at Fmax (160-250Mhz) I doubt there will be any issues.

Saying that, if it doesn't work for you Boncuk, I could try and re-write the code to make sure everything is synchronous. But seeing as its a frequency counter...we run the risk of getting out of sync and introducing errors in the reading of the input. Lets see how it goes.

Blueteeth

 

[Boncuk]

PLD programming

Hi petrv,

here is the Xilinx parallel port adapter. I wrote some comments into the schematic. Please check.

I also added a low current LED to indicate the presence of VCC. If you think it's unnecessary please let me know. Kicking off a part is no problem.

Hans

 

[petrv]

Nice, but I have already designed one. Have you built the adapter ?