please help on this vhdl code...

hello everyone.... i need a help on the following code. first i will explain the whole problem. it is as below
i need to transfer data from a master to a slave. am doin the interconnect part of it. my master and slave supports 32 bit data n address bus. so at a time i can transmit upto 4 bytes of data. any data which is more than that need to be transmitted more than once. my protocol supports burst transfer. it can transmit upto 128 bytes of data 16 times ie is the size and length respectively. am using the folowing algoritghm...

value <= (size/4) -- since i can transmit only 4 bytes a time

for( i = 0 ; i < length ; i++)
{
for( j = 0 ; j < value ; j++)
{
addr <= data ;]
addr <= addr + 4;
}
addr <= addr+ length;
}

how can this be implemnted in vhdl. am trying this for many weeks. i couldnt find how to proceed. also how can i show the out put. am using xilinx 6.1 and modelsim 5.5... please help me on this. i have written the code like this

for j in 1 to len loop
for i in 1 to value loop
addr <= data;
addr <= addr + 4;
end loop;
addr <= addr + len;
end loop;

it says ' + ' cannot be used in that context. am unable to show the out put also. tell me what should i declare addr and data as. i want to see the transition after every 4 bytes of data is transimtted.
i want to see the out put like this.. here length = 2 and size = 16bytes

.........____ ______ _____ _____ ____ ______ ______ ______
data <_1__><__2__><__3__ ><__4___><__1__><__2__><__3__ ><__4___>

please help me...

thanking you...
with great regards...

If you are going to put this on a Xilinx CPLD or FPGA, then you will need to replace the for loops with clocked counters. If explicit clock conditioning is missing, sequential code happens in an "instant" of time.

The synthesis software will not allow "in-place" updates of "variables" unless it is conditioned by a clock. In fact, there are no variables in the generated design. There is no computer, CPU, or MCU that "runs" VHDL. There are only registers, which are generated by the "compiler", and they must be explicitly clocked in VHDL.

Only the simulator will act like a computer. The computer-like simulator code (the test bench) must not be part of the primary design code.

Just to show how radically you must change your thinking, the following shows how to sequentially read a 1024 x 8 ROM. Notice there are no for loops, yet it will read every byte in the external ROM and output the data in sequence on the data_out pins.

its not working.... please check this n tell wats wrong in this..

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pro is
port (clk:in std_logic;
a:inout integer:=0);
end pro;
architecture Behavioral of pro is
signal y,x :integer;
begin
process(clk)
begin
for i in 0 to 4 loop
if(clk'event and clk='1' and a<=10)then
for j in 0 to 8 loop
y <=a ;
x<=a+1;
a<=a+1;
end loop ;
else null;
end if;
end loop;
end process;

end Behavioral; delete



when i work out this code it says

Signal y cannot be synthesized, bad synchronous description.

how can i come out of this..... plz help me.....

Use the code directly in the simulator.

You will not be able to synthesize (create a bit file) for several reasons. As a start, the synthesis software does not treat the for loop as a sequencing command.

If you want to design hardware the same way you design software, VHDL and Verilog are not the tools to use. If you are not able to purchase an ESL tool (which allows you to program hardware as if it were a computer), then you will need to abandon the software approach.

I suggest you start with other designs, such as those published at fpga4fun.com and xess.com.