PLL

[TheOne]

Looks good Ron!

He must just remember the limitations around a XOR detector when using this.

1/ When the ref and vco have the same duty cycle, no problem
2/ Phase shift of pi/2 will result in output of twice the frequency
3/ With different duty cycles you start to have problems. If this is also used with a divide by N counter the output voltage can sometimes be the same for 2 different phase errors due to the duty cycle and narrow pulses out of the divide by N counter. This can be compensated for to some degree by adding a pulse stretcher stage.
So this will work well as long as the ref and vco frequencies are fairly high and not to far apart.

 

[Peter Mortensen]

Here is a PLL I cranked out that has no ICs, and only one type of transistor. <snip>

It is not easy to see some of the component values on the schematics, e.g. for C1 and C2.

Looking into the netlist, C1 and C2 are both 10 nF: "... SYMATTR InstName C2 SYMATTR Value 10n ..."

That would suggest a VCO frequency on the order of 10 kHz. With only +/- 20% variation possible. Am I wrong?


C4 and C6 are also 10 nF.

 

[JimB]

Holy thread resurrections Batman! Thirteen years +

Roff has not visited the forum for 18 months or so, whether he is lurking and will see this I do not know.

That would suggest a VCO frequency on the order of 10 kHz. With only +/- 20% variation possible. Am I wrong?

Probably not, I have not sat down and done any calculations on the oscillators, but I suggest that this was just something knocked up quickly for the benefit of mstecha who started this thread.

It should be noted that mstecha was never inclined to do things the easy way, the more convoluted the better!

Welcome to ETO.

JimB

 

[DerStrom8]

Hi Peter, welcome to ETO!

Guessing you're the same Peter Mortensen I see all the time at EESE?

Best,
Matt

 

[Peter Mortensen]

Hi Peter, welcome to ETO!

Guessing you're the same Peter Mortensen I see all the time at EESE?

Best,
Matt

Yes, that is right.


I am actually going to try to build the VCO part (while waiting for a CD4046), but instead running at
about 2 MHz, lower resistor values (220 ohm for R3 and R6, 1 kohm for R1 and R4, also 1 kohm
for R2 and R5 for wider frequency range), lower capacitor values (500 pF), BC547B, and decoupling
of the supply voltage. Is there a reason this would not work?


Why, you may ask. This is partly yak shaving and partly to learn something...

 

[unclejed613]

there were a few PLLs in TVs. the horizontal oscillator, vertical oscillator, the AFC circuit in the tuner, and the chroma oscillator were all examples of a PLL. sometimes the horizontal and vertical oscillators were oscillators with a sync pulse input, but on later TVs PLLs worked better. but the chroma oscillator was always a PLL, and the AFC in the tuner was also a PLL.

 

[Nigel Goodwin]

there were a few PLLs in TVs. the horizontal oscillator, vertical oscillator.

Horizontal oscillator 'yes', frame oscillator 'no' - except perhaps on later IC based ones?, where it might have been done simply because it was easier to inside an IC, even if it produced no actual benefit.

The horizontal oscillator though benefited greatly from a PLL, and it was called 'flywheel sync' - back before the term PLL existed

 

[schmitt trigger]

Wasn't the synchrodyne, one of the earliest versions of PLLs?

 

[unclejed613]

yes, the synchrodyne receiver did use a PLL to demodulate AM. the PLL kept the detector (in this case, a balanced modulator/analog multiplier) phase locked on the received signal. the synchrodyne could pick signals out from below the noise floor (either -3db or -6db, i forget which). somewhere in the 70s or 80s, there was renewed interest in the principles of the synchrodyne, with a new name "direct conversion" receivers. balanced modulators also became the basis of SSB (single sideband) transmitters and receivers (the difference being they aren't phase locked to the carrier, because SSB discards the carrier). balanced modulators are also used a lot in software defined radios for conversion of RF to baseband, and the separation of the signal into I and Q signals for the DACs