Power Mosfet behaviour

[Esmat]

I am trying to use the p channel power mosfet IRF9540 to switch between transformer and battery inputs. The transformer voltage of 9 V is applied to the gate. The same transformer line pass by a diode and the diode output is applied to the drain, that is the drain voltage is 8.2 V. If the source is not connected to anything then its voltage measurement is 7.7V. If the source is connected to a 6V battery, the Mosfet will overcharge the battery. In both cases the Mosfet is conducting. What I dont understand is that in either case VGS>0 which means that the mosfet should be in a cutoff mode. This area is new to me, and it is appreciated if there is a simple explanation. Thank you.

Esmat

 

[crutschow]

Can't tell what's wrong from your description. Please post a schematic.

 

[Esmat]

I created the schematic with the expressPCB tool but I can't figure how to attach the schematic. What is the way to post it?

 

[BrownOut]

Hit "Go Advanced" at the bottom of the text entry window. Then click on the paperclip icon at the top. Browse for your schematic, then upload.

 

[MikeMl]

Create a PNG, JPG or PDF.

I, and most other folks can't read proprietary formats like Express....

 

[Esmat]

MOSFET Schematic

Herein the schematic of the P channel MOSFET.

 

[crutschow]

Your schematic shows an N-MOSFET.

 

[Esmat]

MOSFET schematics

Sorry for the wrong drawing. I am attaching a file with the correct schematics. Please notice that the attachment comprises 2 schematics for the 2 tests that I have carried out. Thanks.

 

[MikeMl]

It looks to me that you have the PMOS upside down (source and drain reversed). Current will always flow because the SD diode is always forward biased.

 

[Esmat]

Mike, Thank you for your feedback. I understand you that the Source and drain are reversed. I am just curious about why in this particular arrangement that the MOSFET is conducting even though VGS>0. Thanks again.

 

[MikeMl]

Mike, Thank you for your feedback. I understand you that the Source and drain are reversed. I am just curious about why in this particular arrangement that the MOSFET is conducting even though VGS>0. Thanks again.

The PFET isn't conducting; the intrinsic diode inside the PFET is forward biased, so it conducts. If the S & D were reversed, the diode be reversed-biased, so would not conduct, allowing the current from S to D to be controlled by the G-S voltage. However, as you have it hooked up, if you reverse S & D, no current will flow through the PFET, because Vgs is zero.