Preamble detection, how does it happen ?

[kellogs]

Consider two Manchester bits "00" = "0101" symbols as the preamble. Binary FSK modulation. When there is no signal (i.e. only noise on the channel) I envision the average sub-GHz receiver to immediately detect such preamble, because white noise will only yield 0/1 sequences of various lengths.

But this does not happen, no receiver detects such preambles from white noise. So how do they do it ?

 

[rjenkinsgb]

The preamble exists to allow the recovery clock to synchronise with the data. That is all it is for.

In eg. 10Mbit Ethernet, the preamble is seven bytes long, alternating 1 & 0 bits. That allows the PLL to get in lock, for the actual data that follows

There must then be a start of frame sync pattern to mark the start of the actual data, as the PLL would not get in lock until some random way through the preamble.

At the end of a packet or data frame there will be a CRC of the data content. If that is not valid for the overall packet in the decoder, the data is discarded. Likewise if the structure of the data content is invalid.

Example:

ETHERNET FRAME FORMAT

(A receiver also likely uses squelch or RSSI and ignores anything with a carrier strength below a certain level).

 

[Papabravo]

A sequence of bits can be shifted into a register one bit at a time up to some maximum length. A bit string comparator can monitor the bits in the shift register and indicate if the pattern matches the desired preamble. This works well for irregular preambles. You can also use a state machine, either Mealy or Moore, to recognize strings of bits described by a regular expression. This works well for very long preambles with a regular pattern.

In some coding schemes you can also recognize code violations as part of a preamble. This is a really cool thing.

 

[Tony Stewart]

The simplest non-PLL clock recovery for a Manchester code of 0.5T and 1T is to use an XOR edge detector to trigger a 0.75T one-shot. This synchronizes immediately while the PLL that follows that trailing edge of 0.75T reduces the clock jitter. to then sample the data.

For low SNR situations dual integrate and dump methods are used to integrate the pattern of the data relative to the synchronized clock.

If you are talking about async. burst data with a 2 bit preamble, then no PLL is used. Just the circuit I described. However if the clock frequency error is very low, a digital 1-shot using a high clock and divide by N with a reset may be more accurate than an RC one shot with a constant current source.

So define your pattern with clock sync, data sync, word sync, frame sync and include parity or Hamming code or CRC or ECC. Then define worst case SNR and expected BER.