problems with Spartan FPGA

[spark]

i'm doing a final year undergraduate project, part of which involves implementing an adder on a Spartan FPGA. I'm using the ADSU8 adder from the library. The problem is, when i tie 'ADD' to Vcc and carry-in to GND, i'm not getting good results, even though it simulates fine. any ideas?

 

[Styx]

whats your VHDL code?

 

[spark]

I'm using schematic entry at the moment while the design is relatively simple.

 

[Optikon]

i'm doing a final year undergraduate project, part of which involves implementing an adder on a Spartan FPGA. I'm using the ADSU8 adder from the library. The problem is, when i tie 'ADD' to Vcc and carry-in to GND, i'm not getting good results, even though it simulates fine. any ideas?

Elaborate more on not getting "good results."

It doesnt give right output? Sometimes it's right sometimes not?

Did you verify that this component did not get optimized away?