Hi,
Thanks for the diagrams,
they are pretty much as i would have thought,
except that they appear to be for four bit bytes,
unless they just drew four to represent eight,
and you have to imagine the remaining four ?
The second diagram is the one for taking serial in
and delivering parallel out, S.I.P.O.
In my mind it takes the form of the clock pulses
moving the incoming bits along one at a time,
then after eight counts, emptying them sideways into
a latch, and enabling the latch output until the
next serial pulse. (or something very similar)
I don't think the shift register needs to be re-set
as they all move along, the one at the end is lost.
With the opposite function, that is, parallel in to
serial out, the information can come in much faster
than it can be passed on, so some form of buffering
may need to be used.
Also the shift register may need to be reset after
each operation, as it may not necessarily put a zero
into locations that are 'clocked along'.
By that i mean that after the eight counts have moved
along to serial out, and the shift register is ready
to receive another eight bits, then it may not
necessarily have its locations at zero.
The incoming broadside eight bit byte would usually
transfer ones into the shift register.
It may well not transfer zeros, unless its totem-
poled. This would mean that care should be taken to
zero the shift register before the transfer of ones.
Just read up on the various chips you could use, you
will soon get the idea.
Best of luck with it,
John