Shifting large amounts of data around

[3v0]

In order to prioritize all the inputs all the data is going to have to end up on one chip, so one chip per input stream would be a bad idea, but two dual UART chips with a high speed SPI bus to share the UARTS would be ideal.

I would like to understand your reasoning.

Why would all the data/packets have to end up on one chip to determine to determine priority?

 

[Sceadwian]

He wants to take all four of the latest 513 byte packets for each channel compare each byte from each packet and transmit the highest byte per channel on one master channel out. How would you do that on four seperate processors and send the data to a fifth when all the streams are coming in asynchronously? In order to do a compare of four bytes to determine which is greater all four data packets have to be in one spot, and you're talking about comparing four sets of 513 byte packets. I forget you can even get simple bare bones UARTS's. An Atmega16 I think can handle SPI transfers at 8mbits, that's more than enough to keep up with 500kbits of data (two of the UARTS would be SPI the other two would be internal hardware)

 

[bh00]

So as I see it at the moment there are several avenues to go down:
- Multiple PIC design using individual chips per input and one for the output with the output one polling the input chips to send their data to it.
- Multiple PIC design using two chips with dual UARTs sharing their data (although wouldn't a 5th UART be needed to do the outputting?)
- Go for a higher spec PIC (33F?) and work with that
- Look into Amtel chips which isn't something I've used before.

I'm not sure at the moment if I'd be better off trying to accomplish this in assembly or some sort of higher level language as well.

Cheers

 

[philba]

You left off the one that i would persue - multiple UARTs with a single PIC as the traffic cop to and from SRAM. I believe you can come up with a design that does not need to centralize the data in one processor.

On the higher spec approach, you might want to take a look at the Renesas line of micros. the 16 series has several versions that are designed to hook directly to SRAM and have built-in DMA controllers. Though, they may have enough internal RAM to handle your application and thus not need external RAM. iirc, there is at least one with 4 usarts built in. Good speed, 16 bit operations and Decent C support.

how much assembler programming have done to date? If you've got decent experience in asm on any machine, then it won't be a stretch but if you have done very little, I'd stay away from it as you are significantly increasing your overall learning curve. I know other will disagree but you know yourself best.

 

[Pommie]

The only way I can see that this can be done would be to do it for two streams. A single processor comparing 2 streams and outputting the 1 combined stream could be cascaded to do 4 - 2 - 1 using three chips.

Mike.