Shoot-through avoidance technique in LTC3813 synchronous boost converter is dubious?

[Flyback]

Page 12 (LHS) of the following datasheet (below) says that the gate of the lower fet in the synchronous boost should be driven to –2V so that it doesn’t get induced ON when the top (synchronous) fet turns ON. (it says that this is how shoot-through is avoided)
Surely this is not correct?
I mean, by the time the top (synchronous) fet turns on, the drain voltage has already risen to vout + v(diode).
By ”v(diode)”, I am referring to the schottky diode that goes from drain to source of the top fet.

LTC3813 (synchronous boost controller) Datasheet:-
https://cds.linear.com/docs/en/datasheet/3813fb.pdf

Do you agree that there is no shoot-through problem between top and bottom fets since the top fet is never turned on when the bottom fet is on, and there is no shoot-through when the top fet turns on either?

 

[Diver300]

I think that the shoot-through that they are trying to avoid is not really to do with the top FET at all, although the datasheet wording implies that it is. It says "When the top MOSFET turns on", but I think that is actually means "When the bottom MOSFET turns off", although the time difference will be in nanoseconds.

When the lower MOSFET turns off, the drain voltage rises rapidly. That rise causes an effective rise in the gate voltage because of the Miller capacitance, and if that causes the lower MOSFET to fail to turn off, or to turn off slowly, there will be a lot of shoot-though current. The IC manufacturer has allowed the MOSFET gate to be driven lower than ground to give a larger voltage margin between the drive voltage and the MOSFET's gate threshold voltage. This larger voltage margin will mean that the MOSFET turns off faster.

 

[simonbramble]

Firstly, it is not the Source of the lower FET that is held at -2V, but the negative pin of the lower FET *driver* that is held at -2V

Here goes... When the bottom FET turns ON, the drain of the bottom FET is clamped to zero volts and the current ramps in the inductor. When the bottom FET turns off, the drain (as you say) shoots high and the body diode of the synchronous FET turns on. Moments later the drive to the synchronous FET turns on and the FET bypasses its own body diode, thus reducing the losses in the rectifier element (the body diode). This gives the benefits of higher efficiency over a standard boost with just a diode for the rectifier.

However, if you have a strong gate drive for the top FET, it can sometimes put a sharp rising edge on the Gate of the top FET (which is what you want) which then puts a sharp rising edge on the Source of the top FET. This is coupled through the Miller capacitance (the gate-drain capacitance) of the bottom FET which can put a sharp spike on the Gate of the lower FET, thus turning it back on again, when the top FET has just turned on. This is shoot through.

If you put a negative voltage on the bottom FET driver, this holds the Gate of the bottom FET at a negative voltage when OFF, so the spike has to have a much high amplitude to turn on the bottom FET.

This is the idea behind putting a negative bias voltage on the lower FET to hold it firmly off

 

[Flyback]

Woops, my apologies Simon Bramble, I have edited out that clerical error of my top post now, and now have removed that mistaken reference to the source.

However, if you have a strong gate drive for the top FET, it can sometimes put a sharp rising edge on the Gate of the top FET (which is what you want) which then puts a sharp rising edge on the Source of the top FET. This is coupled through the Miller capacitance (the gate-drain capacitance) of the bottom FET which can put a sharp spike on the Gate of the lower FET, thus turning it back on again, when the top FET has just turned on. This is shoot through.

.....thanks, but by the time the top fet is being switched on, the bottom fet's gate has long gone through its miller region. Also, when the top fet turns on, the bottom fet has Vds(off) across it, and so its DS capacitance (and DG capacitance) is small. There is no miller charging going on in the bottom fet when the top fet turns on.

I think you are referring to operation without a parallel schottky across the top fet?....I must confess that I always operate synchronous boost with a schottky across the top fet....and this was always done in a global lighting company that I worked at........since the top fet is turned on when its DS voltage has already been shorted by the schottky to 0.5V...the top fet gate driver sees no miller charge region I am sure you agree with this.......the top fet only has to turn off quickly, it doesn't have to turn on quickly as the turn-on switching losses for the top fet are minimal since its already been shorted by the parallel schottky.........If we are worried by a rapidly rising gate voltage of the top fet, then we should use a diode and resistor there so that the top fet turns on (relatively) slowly and turns off quickly.

 

[simonbramble]

Hi Flyback. Yes you are right. The dominant cause of the upward blip on the bottom FET Gate signal is the large dv/dt that occurs on the switch node due to the inductor and not the high dv/dt from the top FET gate drive. Although the 2 events occur within nanoseconds of each other, the back emf from the inductor is the one that causes the miller feedthrough. The top FET driver is floating and connected across the gate-source of the top FET, so should not affect the voltage on the drain of the lower FET. This took some thinking about.

I also recommend putting a Schottky across the rectifier FET of a synchronous boost. This stops the spike occurring on the switch node (which as we have seen can cause shoot through) because of the slow body diode. This also helps to reduce EMI, but also it stops the body diode conducting charge into the substrate of the sync FET... which is energy that has to be removed when the sync FET switches ON, thus reducing the turn on time and reducing the efficiency.

For the same reason, it is advisable to put a Schottky across the bottom FET in a synchronous *buck* converter.

On the same subject, if you have a large amount of output capacitance in a buck converter, a Schottky across the TOP FET is also advisable, since, if the part does not shut down in a disciplined way, the lower FET can sometime keep oscillating, taking charge out of the output cap, charging up the inductor and causing a positive spike at the switch node that blows up the top FET (the buck turns into a boost converter and boosts the output back to the input)

 

[simonbramble]

Ha! LTspice demonstrates this beautifully. Run the Jig file of the LTC3813 and zoom in on the gate drive waveform as the switch node flies positive. You can see the small increase in gate voltage as the switch node dv/dt feeds through the Miller capacitance.

The effect of the top FET gate drive is non existent, proving you are right. Sorry and thanks for the correction

 

[Flyback]

on the contrary, thanks to yourself for investigating. I had already had time to look into this just before posting and before yourself came forward with your valuable contribution. I notice the miller plateau of the bottom fet's gate as the drain voltage flies positive. As you know, this isn't something that can be helped by using a negative gate drive to the bottom fet.
In fact, in the sim here, you can see the top fet's gate actually spiking up just after its first switched off, though again, this isn't remedy-able by using a negative drive to the top fet gate as that can't be done to the top gate drive.
Anyway, very good chip, constant off time, synchronous, and very low sense voltage reference.