Hi Flyback. Yes you are right. The dominant cause of the upward blip on the bottom FET Gate signal is the large dv/dt that occurs on the switch node due to the inductor and not the high dv/dt from the top FET gate drive. Although the 2 events occur within nanoseconds of each other, the back emf from the inductor is the one that causes the miller feedthrough. The top FET driver is floating and connected across the gate-source of the top FET, so should not affect the voltage on the drain of the lower FET. This took some thinking about.
I also recommend putting a Schottky across the rectifier FET of a synchronous boost. This stops the spike occurring on the switch node (which as we have seen can cause shoot through) because of the slow body diode. This also helps to reduce EMI, but also it stops the body diode conducting charge into the substrate of the sync FET... which is energy that has to be removed when the sync FET switches ON, thus reducing the turn on time and reducing the efficiency.
For the same reason, it is advisable to put a Schottky across the bottom FET in a synchronous *buck* converter.
On the same subject, if you have a large amount of output capacitance in a buck converter, a Schottky across the TOP FET is also advisable, since, if the part does not shut down in a disciplined way, the lower FET can sometime keep oscillating, taking charge out of the output cap, charging up the inductor and causing a positive spike at the switch node that blows up the top FET (the buck turns into a boost converter and boosts the output back to the input)