I didn't see the CPR table at the end of the datasheet, so my math is off. The mechanical limit is 300 RPM, times 32 CPR is 9600 CPM, divided by 60 is 160 Hz, or 3.125 ms per output pulse width, either up or down. I think this makes it even more possible that an overly aggressive debouncer is dropping pulses. With an FPGA, the encoder waveforms could be going into some gates to turn them into clock plus direction signals (which should be fast enough to keep up with anything), or they could go to a firmware CPU core that is executing 8051 or ARM assembler to do the interface in software running on firmware emulating hardware. Gotta love FPGAs.
ak