synchronizing with 1200bps with 32.768kHz clock

[muralikrishna_kn]

PLEASE HELP MEEEEE !!!!!!!!!


If a protocol calls for a data rate of 1200 bits per second, then using a 32.768kHz clock how can I detect the bit boundaries when the incoming data is modulated using FSK?

 

[Nigel Goodwin]

PLEASE HELP MEEEEE !!!!!!!!!


If a protocol calls for a data rate of 1200 bits per second, then using a 32.768kHz clock how can I detect the bit boundaries when the incoming data is modulated using FSK?

Well you don't give ANY details about what you're using or trying to do, so we can only guess?.

But assuming you're running a PIC with a 32KHz clock, that's FAR too slow to do what you want!.

 

[muralikrishna_kn]

Well you don't give ANY details about what you're using or trying to do, so we can only guess?.

But assuming you're running a PIC with a 32KHz clock, that's FAR too slow to do what you want!.

Oh! Sorry about that. Actually, I'm trying to design this using basic digital circuits like counters and flip flops and a few logic gates which are driven by the 32.768kHz clock.

 

[JimB]

Problem 1
Convert the FSK to 1s and 0s using some kind of discriminator or tone decoder.

Problem 2
I am assuming that this is asynchronous serial data rather than just some stream of bits (you did not specify), use a UART.
From your 32khz clock generate the correct clock frequency for the UART.
Put the bit stream from the decoder into the UART.
Watch bytes of data come out of the Data Out pin of the UART.

JimB

 

[Paul Obrien]

it should be possible to dect bit boundries as there aprox 273 cycles per bit, if the bit boundry is all you are trying to detect not FSK demodulation. I have a circuit here somewhere that I have seen only very recently which would work so try google.

 

[muralikrishna_kn]

Could you please give me the link to the site? I'd really like to get my hands on it. But I don't understand what's with 273 cyles per bit??? Could you please elaborate?
Thanks in advance.

 

[Paul Obrien]

32768/1200 is ...whoops 27.3 cycles per bit and normally something like a flip-flop clocked to get get the bit boundry but having a look at your original post you are also after FSK demodulation?? That is trickier. maybe a digital magnitude comparator feed by a shift register, what frequencies involved 1200 & 2200Hz?