synchronous counter design techniques

hi, i have an assignment for my course which asks the following question but as i missed 2 lessons, i dont know how do to it and my tutor won't help me at all so i was wondering if anyone here could help plz?

i need to design a synchronous counter which will produce the count sequence: 2, 3, 5, 1, 7 repeating.

evidence required:

a) state transition diagram. which i have done it's just: 010, 011, 101, 001, 111, 010 in a loop.

b) present state - next state table which i have done but isnt gonna be very easy to read on here:
count present state next state
Qc Qb Qa Qc Qb Qa
0: 0 0 0 0 1 0
2: 0 1 0 1 0 0
4: 1 0 0 1 1 1
7: 1 1 1 0 0 0

c) Draw the truth table, Design Table and Design Map for the flip - flop to be used

d) K - maps for each J and K input

so its c and d i need help with really unless u can spot anything wrong with the first 2 parts. Any help here would be greatly appreciated.

Sate Machines are much easier to design if you break the problem down into parts.

Part 1)
How do you want to encode your states? Remember 2,3,5,1,7 are just the outputs of your state machine - how you represent the states in the machine itself is up to you. You have 5 states here are some posible representations starting with the one you have in question a)

Which one of these is best depends on how you want to implement the machine. 2) would let you use a counter IC for discrete chips. 3) is good for FPGAs because they have tons of registers.

Part 2)
Design the logic for your state transitions. You need combinatorial logic that takes your current state and outputs the new state. This is quite easy for representation 2) and 3). 1) is a bit more dificult but if you draw the truth table and do some boolean algebra you can figure it out.

Part 3)
Decode the state into an output. This is easy for Representation 1) - the state is the output. Its a bit more complicated for 2) and 3) - again just state tables and boolean algebra.

Part 4)
Hook it all together.

I don't know what you're trying to show in b). As far as I can tell from the question it should be the same as your state transitions in your representation.

Questions c) and d) are not very specific so I'm not sure what answer they're looking for.

Hi ant9985

I've designed the synchronous counter which will produce the count sequence: 2, 3, 5, 1, 7 repeating as you want. I've drawned the tables and the circuit, you can see them below. I'm not telling the procedure for now but I think you will get it, if you can't, you can ask to me of course. And my advice to you try not to miss the lessons after this

And here is the circuit... I took +5V here for logical-1, you can choose another suitable value for the parts you use.

Zarkabul , nice job !!
its been a while since i have seen this done so well

If you are going to build this circuit, don't forget to add bypass capacitors.

Len

ok thats great , thank you very much for the help all, especialy zarkabul, that really helped a lot, i appreciate it,

Zarkabul said:

Hi ant9985

I've designed the synchronous counter which will produce the count sequence: 2, 3, 5, 1, 7 repeating as you want. I've drawned the tables and the circuit, you can see them below. I'm not telling the procedure for now but I think you will get it, if you can't, you can ask to me of course. And my advice to you try not to miss the lessons after this

Click to expand...

Do you think the K-Map for Ka has some mistakes? For example, for current state (111) -> next state (010), the Ja and Ka should be X and 1 respectively. Pls advise.

synchronous counter design

I am new to this sight. If anyone is interested in some fresh information on this subject contact me and lets talk. My methods will allow you to design counters using T, D, & JK flip flops. in any conceivable count sequence. you can also mix flip flop types and get the same results. I also have developed simple rule sets for creating binary to gray and gray to binary codes, and ways of generating Karnaugh maps beyond four bits, that are not confusing.

If anyone is interested in some fresh information on this subject contact me and let’s talk. My methods will allow you to design counters using T, D, & JK flip-flops. In any conceivable count sequence. You can also mix flip-flop types and get the same results. I also have developed simple rule sets for creating binary to gray and gray to binary codes, and ways of generating Karnaugh maps beyond four bits, that are not confusing.