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#include "stm32f4xx.h"
void delay(int temp2);
int temp;
void main()
{
GPIOD->MODER = 0x55555555;
GPIOD->OSPEEDR = 0xAAAAAAAA;
GPIOD->PUPDR = 0x00;
GPIOD->OTYPER = 0xFFFF;
while(1)
{
delay(100000);
GPIOD->ODR = 0xFFFF;
delay(100000);
GPIOD->ODR = 0x0000;
}
}
void delay(int temp2)
{
while(temp2--);
}#include "stm32f4xx.h"
void delay(int temp2);
int temp;
void main()
{
RCC->CFGR = 0x80400001;
RCC->AHB1ENR = 0x08;
RCC->CR |= 0x10000;
while(RCC->CR & 0x10000==0);
GPIOD->MODER = 0x55555555;
GPIOD->OSPEEDR = 0xAAAAAAAA;
GPIOD->PUPDR = 0x00;
GPIOD->OTYPER = 0xFFFF;
while(1)
{
delay(500000);
GPIOD->ODR = 0xFFFF;
delay(500000);
GPIOD->ODR = 0x0000;
}
}
void delay(int temp2)
{
while(temp2--);
}#include "stm32f4xx.h" //Include main header for MCU
void delay(int ticks); //Used for delays
void main()
{
//Bits 1:0 (01) HSE oscillator selected as system clock
RCC->CFGR = 0x01;
//Bit 3 GPIODEN: IO port D clock enable (1: IO port D clock enabled)
RCC->AHB1ENR = 0x08;
//Bit 16 HSEON: HSE clock enable (1: HSE oscillator ON)
RCC->CR |= 0x10000;
//Bit 17 HSERDY: HSE clock ready flag (1: HSE oscillator ready)
while(RCC->CR & 0x20000==0);
//GPIO port mode register (all PORTD = 01: General purpose output mode)
GPIOD->MODER = 0x55555555;
//GPIO port speed reg. (all portd = 10: 50 MHz Fast speed)
GPIOD->OSPEEDR = 0xAAAAAAAA;
//GPIO port pull up - pull down reg (00: No pull-up, pull-down)
GPIOD->PUPDR = 0x00;
//0: Output push-pull (reset state)
GPIOD->OTYPER = 0x00;
while(1)
{
//My Crap Delay (~500,000 clks)
delay(500000);
//GPIO port output data register (ALL HIGH)
GPIOD->ODR = 0xFFFF;
//My Crap Delay (~500,000 clks)
delay(500000);
//GPIO port output data register (ALL LOW)
GPIOD->ODR = 0x0000;
}
}
void delay(int ticks)
{
while(ticks--);
}
#ifndef stm32f407_h
#define stm32f407_h
//------------------------------
// RCC_CR Definitions
//------------------------------
#define PLLI2SRDY 0x8000000 //PLLI2S clock ready flag
#define PLLI2ISON 0x4000000 //PLLI2S enable
#define PLLRDY 0x2000000 //Main PLL (PLL) clock ready flag
#define PLLON 0x1000000 //Main PLL (PLL) enable
#define CSSON 0x80000 //Clock security system enable
#define HSEBYP 0x40000 //HSE clock bypass
#define HSERDY 0x20000 //HSE clock ready flag
#define HSEON 0x10000 //HSE clock enable
#define HSIRDY 0x2 //Internal high-speed clock ready flag
#define HSION 0x1 //Internal high-speed clock enable
//------------------------------
// RCC_CFGR Definitions
//------------------------------
//MCO2[1:0]: Microcontroller clock output 2
#define MCO2_SYSCLK 0x00000000 //System clock (SYSCLK) selected
#define MCO2_PLLI2S 0x40000000 //PLLI2S clock selected
#define MCO2_HSE 0x80000000 //HSE oscillator clock selected
#define MCO2_PLL 0xC0000000 //PLL clock selected
//MCO2PRE: MCO2 prescaler
#define MCO2PRE_2 0x20000000 //division by 2
#define MCO2PRE_3 0x28000000 //division by 3
#define MCO2PRE_4 0x30000000 //division by 4
#define MCO2PRE_5 0x38000000 //division by 5
//MCO1PRE: MCO1 prescaler
#define MCO1PRE_2 0x4000000 //division by 2
#define MCO1PRE_3 0x5000000 //division by 3
#define MCO1PRE_4 0x6000000 //division by 4
#define MCO1PRE_5 0x7000000 //division by 5
//I2SSRC: I2S clock selection
#define I2SSRC_PLLI2S 0x00 //PLLI2S clock used as I2S clock source
#define I2SSRC_ECLK 0x800000 //External clock mapped on the I2S_CKIN pin used as I2S clock source
//MCO1: Microcontroller clock output 1
#define MCO1_HSI 0x00 //HSI clock selected
#define MCO1_LSE 0x200000 //LSE oscillator selected
#define MCO1_HSE 0x400000 //HSE oscillator clock selected
#define MCO1_PLL 0x600000 //PLL clock selected
//RTCPRE: HSE division factor for RTC clock - Must be 1MHZ
#define RTCPRE 0x10000 //USE THIS VALUE TO SHIFT 2 to 31 EX: if HSE = 8Mhz then use (8<<RTCPRE) (0 or 1 - NO CLOCK)
//PPRE2: APB high-speed prescaler (APB2)
#define PPRE2_DIV0 0x00 //AHB clock not divided
#define PPRE2_DIV2 0x8000 //AHB clock divided by 2
#define PPRE2_DIV4 0xA000 //AHB clock divided by 4
#define PPRE2_DIV8 0xC000 //AHB clock divided by 8
#define PPRE2_DIV16 0xE000 //AHB clock divided by 16
//PPRE1: APB Low speed prescaler (APB1)
#define PPRE1_DIV0 0x00 //AHB clock not divided
#define PPRE1_DIV2 0x1000 //AHB clock divided by 2
#define PPRE1_DIV4 0x1400 //AHB clock divided by 4
#define PPRE1_DIV8 0x1800 //AHB clock divided by 8
#define PPRE1_DIV16 0x1C00 //AHB clock divided by 16
#endif#ifndef stm32f407_h
#define stm32f407_h
//----------------------------------------------------------
// RCC clock control register (RCC_CR)
//----------------------------------------------------------
#define PLLI2SRDY 0x8000000 //PLLI2S clock ready flag
#define PLLI2ISON 0x4000000 //PLLI2S enable
#define PLLRDY 0x2000000 //Main PLL (PLL) clock ready flag
#define PLLON 0x1000000 //Main PLL (PLL) enable
#define CSSON 0x80000 //Clock security system enable
#define HSEBYP 0x40000 //HSE clock bypass
#define HSERDY 0x20000 //HSE clock ready flag
#define HSEON 0x10000 //HSE clock enable
#define HSIRDY 0x2 //Internal high-speed clock ready flag
#define HSION 0x1 //Internal high-speed clock enable
//----------------------------------------------------------
// RCC PLL configuration register (RCC_PLLCFGR)
//----------------------------------------------------------
//ADD IT HERE
//----------------------------------------------------------
// RCC clock configuration register (RCC_CFGR)
//----------------------------------------------------------
//MCO2[1:0]: Microcontroller clock output 2
#define MCO2_SYSCLK 0x00000000 //System clock (SYSCLK) selected
#define MCO2_PLLI2S 0x40000000 //PLLI2S clock selected
#define MCO2_HSE 0x80000000 //HSE oscillator clock selected
#define MCO2_PLL 0xC0000000 //PLL clock selected
//MCO2PRE: MCO2 prescaler
#define MCO2PRE_2 0x20000000 //division by 2
#define MCO2PRE_3 0x28000000 //division by 3
#define MCO2PRE_4 0x30000000 //division by 4
#define MCO2PRE_5 0x38000000 //division by 5
//MCO1PRE: MCO1 prescaler
#define MCO1PRE_2 0x4000000 //division by 2
#define MCO1PRE_3 0x5000000 //division by 3
#define MCO1PRE_4 0x6000000 //division by 4
#define MCO1PRE_5 0x7000000 //division by 5
//I2SSRC: I2S clock selection
#define I2SSRC_PLLI2S 0x00 //PLLI2S clock used as I2S clock source
#define I2SSRC_ECLK 0x800000 //External clock mapped on the I2S_CKIN pin used as I2S clock source
//MCO1: Microcontroller clock output 1
#define MCO1_HSI 0x00 //HSI clock selected
#define MCO1_LSE 0x200000 //LSE oscillator selected
#define MCO1_HSE 0x400000 //HSE oscillator clock selected
#define MCO1_PLL 0x600000 //PLL clock selected
//RTCPRE: HSE division factor for RTC clock - Must be 1MHZ
#define RTCPRE 0x10000 //USE THIS VALUE TO SHIFT 2 to 31 EX: if HSE = 8Mhz then use (8<<RTCPRE) (0 or 1 - NO CLOCK)
//PPRE2: APB high-speed prescaler (APB2)
#define PPRE2_DIV0 0x00 //AHB clock not divided
#define PPRE2_DIV2 0x8000 //AHB clock divided by 2
#define PPRE2_DIV4 0xA000 //AHB clock divided by 4
#define PPRE2_DIV8 0xC000 //AHB clock divided by 8
#define PPRE2_DIV16 0xE000 //AHB clock divided by 16
//PPRE1: APB Low speed prescaler (APB1)
#define PPRE1_DIV0 0x00 //AHB clock not divided
#define PPRE1_DIV2 0x1000 //AHB clock divided by 2
#define PPRE1_DIV4 0x1400 //AHB clock divided by 4
#define PPRE1_DIV8 0x1800 //AHB clock divided by 8
#define PPRE1_DIV16 0x1C00 //AHB clock divided by 16
//HPRE: AHB prescaler
//Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after HPRE write.
//Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
#define HPRE_DIV0 0x00 //0xxx: system clock not divided
#define HPRE_DIV2 0x80 //system clock divided by 2
#define HPRE_DIV4 0x90 //system clock divided by 4
#define HPRE_DIV8 0xA0 //system clock divided by 8
#define HPRE_DIV16 0xB0 //system clock divided by 16
#define HPRE_DIV64 0xC0 //system clock divided by 64
#define HPRE_DIV128 0xD0 //system clock divided by 128
#define HPRE_DIV256 0xE0 //system clock divided by 256
#define HPRE_DIV512 0xF0 //system clock divided by 512
//----------------------------------------------------------
// RCC clock interrupt register (RCC_CIR)
//----------------------------------------------------------
//CSSC: Clock security system interrupt clear
#define CSSC_CLR 0x800000 //Clock security system interrupt clear - This bit is set by software to clear the CSSF flag.
#define PLLI2SRDYC 0x200000 //PLLI2S ready interrupt clear - This bit is set by software to clear the PLLI2SRDYF flag.
#define PLLRDYC 0x100000 //Main PLL(PLL) ready interrupt clear - This bit is set by software to clear the PLLRDYF flag.
#define HSERDYC 0x80000 //HSE ready interrupt clear - This bit is set by software to clear the HSERDYF flag
#define HSIRDYC 0x40000 //HSI ready interrupt clear - This bit is set by software to clear the HSIRDYF flag
#define LSERDYC 0x30000 //LSE ready interrupt clear - This bit is set by software to clear the LSERDYF flag
#define LSIRDYC 0x10000 //LSI ready interrupt clear - This bit is set by software to clear the LSIRDYF flag
#define PLLI2SRDYIE_ON 0x2000 //PLLI2S ready interrupt enable - Set and cleared by software to enable/disable interrupt caused by PLLI2S lock
#define PLLRDYIE 0x1000 //Main PLL (PLL) ready interrupt enable - Set and cleared by software to enable/disable interrupt caused by PLL lock.
#define HSERDYIE 0x800 //HSE ready interrupt enable - Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
#define HSIRDYIE 0x400 //HSI ready interrupt enable - Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization.
#define LSERDYIE 0x200 //LSE ready interrupt enable - Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.
#define LSIRDYIE 0x100 //LSI ready interrupt enable - Set and cleared by software to enable/disable interrupt caused by LSI oscillator stabilization.
#define CSSF 0x80 //Clock security system interrupt flag - Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit.
#define PLLI2SRDYF 0x20 //PLLI2S ready interrupt flag - Set by hardware when the PLLI2S locks and PLLI2SRDYDIE is set. Cleared by software setting the PLLRI2SDYC bit.
#define PLLRDYF 0x10 //Main PLL (PLL) ready interrupt flag. Set by hardware when PLL locks and PLLRDYDIE is set.Cleared by software setting the PLLRDYC bit.
#define HSERDYF 0x08 //HSE ready interrupt flag. Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set.Cleared by software setting the HSERDYC bit.
#define HSIRDYF 0x04 //HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set.
#define LSERDYF 0x02 //LSE ready interrupt flag Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is set
#define LSIRDYF 0x01 //LSI ready interrupt flag Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit.
//----------------------------------------------------------
// RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
//----------------------------------------------------------
#define OTGHSRST 0x20000000 //USB OTG HS module reset Set and cleared by software.
#define ETHMACRST 0x2000000 //Ethernet MAC reset Set and cleared by software.
#define DMA2RST 0x400000 //DMA2 reset Set and cleared by software.
#define DMA1RST 0x200000 //DMA2 reset Set and cleared by software.
#define CRCRST 0x1000 //CRC reset Set and cleared by software.
#define GPIOIRST 0x100 //IO port I reset Set and cleared by software.
#define GPIOHRST 0x80 //IO port H reset Set and cleared by software.
#define GPIOGRST 0x40 //IO port G reset Set and cleared by software.
#define GPIOFRST 0x20 //IO port F reset Set and cleared by software.
#define GPIOERST 0x10 //IO port E reset Set and cleared by software.
#define GPIODRST 0x08 //IO port D reset Set and cleared by software.
#define GPIOCRST 0x04 //IO port C reset Set and cleared by software.
#define GPIOBRST 0x02 //IO port B reset Set and cleared by software.
#define GPIOARST 0x01 //IO port A reset Set and cleared by software.
#endif
