The slave device needs to be configured for "slave mode" in its own program.
That configures it so the SPI shift register clock pin is an input rather than an output, allowing the master device to clock data in to the slave's shift register.
The slave device needs to be configured for "slave mode" in its own program.
That configures it so the SPI shift register clock pin is an input rather than an output, allowing the master device to clock data in to the slave's shift register.
Hi M,
Is it possible then that the MASTER can receive DATA from the SLAVE?
EDIT: I've just realised something!!! The master is receiving DATA from all the other SLAVES, and the second PIC is simply another SLAVE. (Is this true?)
C.
Hi,
Well I've tried for weeks now, and with SPI between two different type of PIC, while being confused by the SPI/I2C choices, I've realised that this is much too difficult for my skills.
Hi M,
Is it possible then that the MASTER can receive DATA from the SLAVE?
EDIT: I've just realised something!!! The master is receiving DATA from all the other SLAVES, and the second PIC is simply another SLAVE. (Is this true?)
C.
Hi N,
I misnamed it SLAVE, what I should have called it is AZIMUTH on a SLAVE PIC. (Now changed)
Each of the SLAVEs has a C/S including the SLAVE PIC.
C.
If you can tell us what is not work it might help. I think you are talking to SPI slave ICs. It is just the micro(slave) is not responding.
I get confused by which pin is data in or data out in slave mode. Does Dout need to be configured as out first. Dose the clock source need to be set as external or is that automatic in slave mode.
If you can tell us what is not work it might help. I think you are talking to SPI slave ICs. It is just the micro(slave) is not responding.
I get confused by which pin is data in or data out in slave mode. Does Dout need to be configured as out first. Dose the clock source need to be set as external or is that automatic in slave mode.
Hi R,
I'm pretty sure the SLAVE PIC is working. I have two buttons to simulate quadrature counting, and I have put this in memory then READ it and out putted it via HSEROUT, that I can see on a computer terminal.
The MASTER is READing the memories of the external modules, but they have REGISTERs with BYTE sized addresses that are READ successfully. So far I haven't been able to put the AZIMUTH into a BYTE sized area.
The TRISs need to be set accordingly.
MASTER OUT SLAVE IN = MOSI on the D/S it says e,g, SDO of the MASTER and SDI on the SLAVE.
The CLOCK of the MASTER must = OUT and the SLAVE = IN, THE SLAVE uses the MASTER clock.
I'm now testing the SPI OUTPUTs with a digital analyser, but some of the connections aren't working???
By "package" I mean that you can get the PIC18F4620 in a 28 pin dip (soic), a 40 pin dip (soic) or a 44 pin TQFN.
That means that some pins are not there in the different packages (i.e. a 28 pin dip won't have as many pins as a 44 pin TQFN).
So, functionality gets moved around, depending on the package.
From what I'm seeing, the PIC18LF4431 is a 3.3v device and the PIC18F4620 is a 5v device.
Could there be some kind of level shifting needed?
Voltages aren't 'set in stone', a 5V PIC works perfectly well at 3.3V - I've always thought there's little point in using the LF series devices, the normal F series go plenty low enough.