transmitting & receiving data

Hello guys, this is the first time that I post here in this website so I hope it will be a good beginning ,
My mini project is about " transmitting & receiving data " , the system I am going to implement is as shown in the figure below , have a time to look on it….
All right, the explanation :
This system is consists of 1-data to be transmitted
2-multiplexer
3-transmission media ( assuming some delay)
4- demultiplexer .
5- the receiver's clock initiator ( the ? block diagram )
& finally 6- the output monitors (" lamps speakers ,or any thing")
The idea of this system is as simple as it , only transmitting data using multiplexer , the data I want to transmit consists of 16 input (16 bit) ( in the sketch I only used 4 input as a beginning ), since the clock at the receiver has to be synchronized with the data received ,
I have decided to make the first input (the first transmitting bit ) always 1 ,
So the clock only be operated if the bit 1 just been received ,
My problem is what is the components that make the clock at the receiver works as that ,
if I used a group of one shot it will need more than 5 of them to do that, until that there will be no synchronizing at all, because of the delay between the clock and the data received & delay accumulation …..
so please help me to find out the best connection for my project .
photon
2105006 .

Try this circuit. It will set when the start bit comes in, allowing your counter to clock, and provides an input to reset it when all the bits are received. You provide that input to reset it, either by decoding the highest count from your counter, or from the highest bit on your demux.

Left for you is to find the equivalent 74xxx series devices. I show the CMOS 4000 series devices. I already had this circuit made for a very similar project as yours. You may get away without the gates at the bottom. I put them there to provide a delay to clock a latch using the Qnot output of the top flip-flop after all the bits were received. My counter was postive edge triggered and it looks like yours is negative edge triggered, so probably an AND gate should be used at the top instead of a NAND gate.

thank you mr. ccutits for your replying
i will check your circuit & then tell you the result , for the resetting bit , i think the best & the easiest way is to connect an and gate with 4 input to the output of the counter at the receiver , so the output will be 1 only if all output are 1 ( all the data has been selected ) .
wish to me a good luck .

That sounds good photon. Good luck.

Hello mr.ccurtis
Ahhhh! .
Actually I did what you have told me to do ,your circuit was brilliant & awesome ,but unfortunately , for some reasons the cuircuit didn’t work well , I wonder if I made any mistakes , but I don't think so , you can check the connection with your self if you want ,
man i was very close ......
If there is any mistakes or you have any ideas pleas tell me .

Hello again .....
This circuit doesn’t catch with me any way I came from , I did another circuit that gives me 1 just when the first bit has been received and when all data received it Resets the counter preventing any delay accumulation , the same theory for your circuit mr,ccurits (thank u very much) . I have tried hard to make it without any delay .
But it doesn't get work , I post the circuit below , now there is a question before I begin with another circuit designe , does the multisim8 works well ? , theoretically the design is 100% working synchrounizly with the data, I also made a small delay at the input of the demux just to make sure that the data can't advance the clock.
Ps if any one has an idea tell me …… , my head will be explode soon !

Two UARTs, of course, would do what you want much simpler, but I suppose you don't necessarily want "simple".

I look it over, Mr. photon, and get back to you. I've been busy lately. Also, if you are interested, I can post the complete Transmitter and Receiver I did for someone.

Photon, a couple of things I see quickly are:

1. The 74393 counter is a ripple counter, so decoding its output may easily reset my circuit before all the bits are recieved.

2. The output of your mux cannot be active unless both the enable inputs are low. I see that you have only one enable input connected.

The specific problem you are having is not at all clear to me.

Hello mr.Crutschow nice to write to you
Well , I am not interested in a very simple circuit , that is if these two components are really existed in my country and cheap , also our mini project should not be very simple or very complex , I have to make it in the middle , so if you have any idea , I am ready to see it after all of these failed tries .

Hello mr.ccurtis glad to see your reply .
Actually it is my pleasure to accept your offer about your circuit that you had design
I think it will help me somehow.

For my problem …… and let me write this ( ahhhh! ) . that is better .
As you now mr .ccurtis the mux must have enables to select it is input , so my input is 16 bit ( I think I should began with 4bits ) the enables of these inputs is A B C D these input is connected with the counter , when A B C D = 0 0 0 0 the first line will be selected and when
A B C D = 1 0 0 0 the second line will be selected and so on ……. I know you Know these stuffs of course , (the problem is) when I choose to connect the mux to the demux without any delay
The output should be matched with the inputs, If the first input is 1 and the other is 0 , the first output should be 1 and the others should be zeros ……but I don’t know why the result when I did that was …. The first o/p is 1 the second o/p will be 1 too but with a very short time duration ….. that is what made me confused about working at multisim 8 . is it bad or what .
I really think of another solution to my circuit , like I can use 8 separated pins (one by one)to transmit 1 always , and the other separated pins to transmit the inputs I want , then using one shot I can synchronize the clock , but if the simulation works as I told you …. I wonder if it will be success .
Also I don’t have one shot in multisim 8 .

About the decoder that resets the circuit , I really don’t know how to make use of it in my circuit, did you mean by resetting the circuit .. resetting the clock ? if that so your design that you post to me was pretty good theoretically , and with that 4i/p AND gate it can be reset
Like I told you , …so my problem is ……. I don’t know ?!
Hahahaha…… welcome to confusing world !..... I wonder if can I handle this circuit .

there is some mistakes I figured out from the last circuit I post ,
first the NAND gate at the counter in the receiver made the clock to be reset the counter with a very high speed , so I deleted it , I think this will not effect , because the counter will continuous to operate normally , & I have replaced the XOR gate at the clk initiator with an OR gate to prevent any delay, also this will not be effect 'cause the clk will be operate only when the first transmitted bit is received ..the new circuit is below
however ....it looks like the main reasons for my fault is stell the time delay between the clock and the data been transmitted , i have decreased the frequency of the clock to xxx HZ
and i found that there is a delay difference about 1.0xx msec
so my problem is stell existed ,..... hmmmm .......
is n't there an ic that can make this synchronization .....
i begin to think that i can't make 100% synchronization using ffs or gates .....
any idea .....?

Photon, look at the attached circuit. It has been built and simulated. It works in both cases. Regards.

As far as your circuit goes, try using a synchronous counter instead of a ripple counter. A ripple counter generates outputs for brief periods that are other than the output you expect.

Your mux is always outputting data with a logic one in it, also. Your transmitter should output a word and then stop by going all zeros for a while before outputting another word. There is no way for the receiver to know if a high bit is a start bit, or a bit within a word if your transmitter keeps wrapping around itself. This is because your scheme (and mine) has no stop bit. The scheme relies on a word having a specific number of bits only, so the words should not run into each other.

I am thinking that in a simulator the two 1MHz clock sources are running in phase, but in a actual circuit the two clocks will not be syncronous. Can you set the two clocks to different phases in the sim file?

Mikebits said:

I am thinking that in a simulator the two 1MHz clock sources are running in phase, but in a actual circuit the two clocks will not be syncronous. Can you set the two clocks to different phases in the sim file?

Click to expand...

This is something you must be aware of photon. Your two clocks are likely changing state at exactly the same time. This does not matter with my circuit, because the receiver's clock has no function until after the start bit is received, after which the next edge of the clock takes effect, and although sychronous with the transmitter's clock after that, can be considered a coincidence only.

IR transmitter and Receiver circuits

hello mr.ccurtis
very well , thank you for posting your circuit designe , you are so kind .

i have seen your circuit , it is a nice idea to replace the mux and the counter with the (parallel to series converter ) ,actually it will do the same function but with decreasing the number of component , and hence the delay .....nice idea .

ok , mr .ccurtis i will check it in multisim program and i hope it will work ,i know it will work but it is kind of testing the program it self .

so plz give me a chance for testing before i write to you .
thank you very much

Hello a gain
Sorry for make you waiting mr.ccurtis , I have implemented the circuit using the multisim 8 ..
I don’t know but ,when I have ran the simulation ,an error massage always came out and says that the timestep is too small , although I followed the instruction to get out from this error but the result was the same , I have posted the circuit if you want to check , any way my friend has a pspice program I will ask him to test the circuit ….as kind of never giving up

The reason of all of these testing is not to be sure that the circuit is working (’cause you write that it works, and it does ) but I can’t work on my program again if it is not working well ( or I don’t know how to use it !!) .
Actually I was surprised , your circuit is a hybrid of genius and brilliant ideas .
So Dr.ccurtis , what do you suggest to make your circuit works as 16 bit transmitter ,and transmitting continuously without pushing to transmit .
You have seen that I used a mux , demux and tried hard ( even after the midnight ) to make it work , but unfortunately it didn’t work .

Photon, I'm sorry to hear about all the trouble. You have indeed tried hard. Attached is a version of my circuit where the transmitter continuously outputs a transmit word. The counter is used as a clock divider. It loads the shift register a few clocks after each time it is emptied. I am using a student version of an unsupported simulator (not multisim), but when I get a timestep error I slow the clock down. I don't recall getting timestep errors in digital simulation mode. Maybe you are including a transient analysis? You can do away with the flip-flop delay thing in your circuit until you get everything working, to simply your circuit, putting in the delay afterwards.

Expanding to 16 bits (and more) is easy. Just add another shift register in the transmitter with the output of one feeding the serial input of the other. Use a higher tap (say, Q9) on the clock divider I added to account for the longer word.

For the receiver, just add more shift registers and more latches, just as you see for my 8 bit receiver, which is 4 bits expanded to 8 already.

Look up Manchester en-de-coding, it embeds the clock signal with the data signal