Turn off switching loss in Active Clamp Forward converter?

[Flyback]

Page 7 (LHS) of the following (below) article is totally wrong, do you agree?

It says that regarding active clamp forward converters, “With sufficiently fast gate drive,
the turn off of Q1 can be virtually lossless.” (Q1 being the main power mosfet).

This is impossible, current cannot suddenly go to zero in Q1 and cannot immediately divert into the clamp capacitor until the drain voltage has risen to V(clamp) + V(diode).
So do you agree that this article is totally wrong in saying that there are no turn off switching losses in the main power fet?


https://www.ti.com/lit/an/snva591/snva591.pdf

 

[MrAl]

Page 7 (LHS) of the following (below) article is totally wrong, do you agree?

It says that regarding active clamp forward converters, “With sufficiently fast gate drive,
the turn off of Q1 can be virtually lossless.” (Q1 being the main power mosfet).

This is impossible, current cannot suddenly go to zero in Q1 and cannot immediately divert into the clamp capacitor until the drain voltage has risen to V(clamp) + V(diode).
So do you agree that this article is totally wrong in saying that there are no turn off switching losses in the main power fet?


https://www.ti.com/lit/an/snva591/snva591.pdf

Hello there,


What you say is true, but they are not saying that.

They are saying that the current is diverted through the drain source capacitance, not the clamp capacitance. Obviously because this capacitance is so small the turn off speed has to be extremely high, hence the 3 amp drive capability of one of their products.

There are two special scenarios that i know of where you can get a transistor to exhibit almost no switching loss.

 

[Flyback]

I disagree with you, they are saying exactly what I said they said, and its totally wrong, You cannot possible get zero dissipation in the switch off transient of Q1, (the main power mosfet).
The drain voltage of Q1 must rise up to {v(clamp) + v(diode)} before the Q1 current can stop flowing in Q1.

 

[alec_t]

“With sufficiently fast gate drive, the turn off of Q1 can be virtually lossless.”

It depends on your/their interpretation of 'virtually'. They could just be referring to the fact that if the time during which the FET is only partly switched on is short then the losses are correspondingly small. You, on the other hand, are interpreting this passage as saying that "there are no turn off switching losses". Not quite the same thing

 

[MrAl]

Hello again,

alec:
Believe it or not, that is another separate issue.

Flyback:
I understand why you would want to think that, but you really should look at the circuit, and that's not how they stated it either.

They specifically mention the "drain to source" capacitance. Did you see that part?

Again what you say is true, but your conclusion i believe is wrong because you are not separating Q1 from it's drain to source capacitance Cds. It is true that current will still flow into the transistor Q1, but that current will no longer encounter an ohmic portion of the die that will cause power dissipation. The part that experiences the current is then considered a true capacitance, and a true capacitance does not dissipate power.

This is really simple to imagine...
Imagine another small external capacitor in parallel with the drain source. If Q1 can turn off then the capacitor will have to handle the current. Of course this comes at a price because when the transistor turns on later it has to discharge that capacitance too.

 

[Flyback]

When Q1 turns off, it does not go from "fully enhanced" to "totally blocking" in zero time.......and therafter current only flows into the cds capacitor.......the current that flows into the cds capacitor is extra current. As the drain voltage of q1 rises up to the clamp capacitor voltage, the full peak primary current flows through the rdson of Q1....yes, current also flows into the cds capacitor, and into the cgd capacitor, but that is a current given by I = c.dv/dt.

The turn off of Q1 has just as much switching loss as it would in a 2 transistor forward converter....and the 2 transistor forward converter is what the active clamp forward converter competes with.

 

[ronsimpson]

I did a active clamp flyback power factor corrector years ago. The power savings was probably not worth the extra parts.

I have done much work where there is an external capacitor across the switch. (CRT/Monitor horizontal) There is a huge advantage to turning off a switch with a cap across it. With a 1200 volt P-P signal. I usually have the switch current down to zero by the time the voltage is 50 volts. Compare that to having 10A in the switch all the way up to 1kv.

I think this active clamp is half way to resonant or qui-resonant where the switching edge losses are low. If you want to see low switching losses head to the resonant side.

 

[crutschow]

I disagree with you, they are saying exactly what I said they said, and its totally wrong, You cannot possible get zero dissipation in the switch off transient of Q1, (the main power mosfet).
The drain voltage of Q1 must rise up to {v(clamp) + v(diode)} before the Q1 current can stop flowing in Q1.

You are beating the wrong horse. They are talking about an active clamp where the clamp transistor turns ON before Q1 turns OFF. Thus there is no v(clamp) or v(diode) voltages. So when Q1 rapidly turns off, its current is diverted to the capacitor before the voltage has a chance to significantly rise. Thus there is very little switching dissipation in Q1 (not ABSOLUTE ZERO, of course, but very low).

 

[Flyback]

sorry but the clamp transistor never turns on whilst the main fet (Q1) is ON,

 

[ronsimpson]

I agree with Crutschow.
See waveform on data sheet. I think both MOSFETs are on at the same time.

 

[MrAl]

When Q1 turns off, it does not go from "fully enhanced" to "totally blocking" in zero time.......and therafter current only flows into the cds capacitor.......the current that flows into the cds capacitor is extra current. As the drain voltage of q1 rises up to the clamp capacitor voltage, the full peak primary current flows through the rdson of Q1....yes, current also flows into the cds capacitor, and into the cgd capacitor, but that is a current given by I = c.dv/dt.

The turn off of Q1 has just as much switching loss as it would in a 2 transistor forward converter....and the 2 transistor forward converter is what the active clamp forward converter competes with.

Hi again,

They are not stating that it goes from on to off in zero time. Here is a direct quote from the paper:

With sufficiently fast gate drive,
the turn off of Q1 can be virtually lossless. To
accomplish this, the gate of Q1 must be turned off
(and the flow of current stopped) before the drain
voltage has a chance to rise. The rise of the drain
voltage is delayed due to the drain-source capacitance;
a robust gate driver can turn off Q1 before
the drain voltage increases significantly. The use of
a compound gate driver made up of MOS and
Bipolar devices provides a high peak gate discharge
current to ensure a fast turn off and reduced
switching losses.

Note the last sentence, "...and reduced switching losses.".

I think you are just taking the previous statement "virtually lossless" too much to heart without considering the entire passage which balances that out a bit.

We have basically a switch, a current source, and a capacitor. The capacitor is in parallel with the switch. The current source feeds the switch and cap. When the switch is on, all the current passes through the switch and the cap voltage is zero. As the switch starts to open it's resistance increases, and the current starts to flow in the cap and the voltage across the cap starts to rise. The instantaneous power in the switch is vC*Iswitch (both functions of time).
It is simple to see that if we can make Iswitch go low fast, vC does not get too long of a time to charge up.
Since the time it takes Iswitch to decrease is directly related to the gate drive current, the more drive current we apply the faster the Iswitch current goes to near zero, and so the less power dissipation.
At some point the total power caused by vC*Iswitch over all time gets lower than some threshold which when compared to the switches overall power dissipation (at other times) turns out to be very very low. That's the point where we have the right gate drive current.
Although it may not be exactly zero, when compared to other power dissipation times in the circuit or even other drive topologies the power profile can be called "virtually lossless".

Please also note that they are talking about a specialized high current driver too, which would provide a huge current for the gate during turnoff.

Another similar scenario is when we turn a MOSFET on for the first time into an inductance. The voltage goes from max to zero in a very short time but the current is near zero so there is "virtually no power dissipation" in the MOSFET. This will happen every cycle in some converters.

 

[Flyback]

you say the cap voltage is zero...but it isn't, its the clamp cap of an active clamp forward converter, and its not zero, its well above zero.....its actually likely to be higher than vin.

If you are saying that the faster a switching transition is in a smps fet, then the less energy is dissipated, then I agree, but that's a feature of any smps topology, this paper is pretending that its only relevant to active clamp forward converters.

 

[crutschow]

you say the cap voltage is zero...but it isn't, its the clamp cap of an active clamp forward converter, and its not zero, its well above zero.....its actually likely to be higher than vin.
..........................

The capacitor clamp voltage is equal to the ON source-drain voltage of Q1 just before it turns off, which is normally less than a volt. Why do you think it's higher than vin??

 

[Flyback]

I guarantee that the voltage across that cap is much above zero...when the fet is on, one side of the cap is zero volts, the other side is far below ground.

 

[ronsimpson]

I guarantee that the voltage across that cap is much above zero...when the fet is on, one side of the cap is zero volts, the other side is far below ground.

And that is why you think it does not work.

 

[Flyback]

that is why I think that at turn off of the fet, the current cannot "immediately" divert into the clamp capacitor.

 

[ronsimpson]

I know it is a different IC. Gate drive waveform. Both FETs are on at the same time.
Note: one of the FETs is a P and so the (actual) gate waveform is inverted from the picture.

 

[ronsimpson]

Here is a data sheet from yet another source.

 

[ronsimpson]

Some waveforms in this one. (two) (three)

 

[alec_t]

Here's a sim comparing use of (a) an active clamp where the clamping FET switch-on leading edge coincides with the main FET switch-off trailing edge with the use of (b) a simple cap across the main FET (as per Ron, post #7). Interestingly the combined losses in the two FETs in a is only slightly less than if the active clamp were omitted; and the loss in b is less than the loss in either FET in a. So is active clamping worthwhile?