Turn off switching loss in Active Clamp Forward converter?

I think above (#17) when you show the gate drives being high and low together, one is for a p fet, and the other is for an n fet, so the fets are not actually on together....Page 778 of Basso's book describes active clamp forward operation.

I think the main advantage of the active clamp forward is the fact that if a p type , low side clamp cap drive is used, then you dont need high side gate drive components at all.

Flyback said:

you say the cap voltage is zero...but it isn't, its the clamp cap of an active clamp forward converter, and its not zero, its well above zero.....its actually likely to be higher than vin.

If you are saying that the faster a switching transition is in a smps fet, then the less energy is dissipated, then I agree, but that's a feature of any smps topology, this paper is pretending that its only relevant to active clamp forward converters.

Click to expand...

Hi,

On that note, i thought that the issue with the drain source capacitance taking the current was separate from the active clamp issue. In other words, we have to discuss these two issues separately because they have different functions. Even though those functions are similar they are not exact.

The quote that i quoted from the paper talked about the issue regarding the drain source capacitance helping the turn off power profile of the MOSFET. To me this fits more into the gate drive characterization of the circuit rather than the "active" clamp character. The reason it would work is because of the gate drive not the active clamp, so you are right about that part. I believe we have to divide the discussion into two parts, the gate drive and the active clamp. I also think you might be a little overly critical of the way it is worded, even though it could be better. Yes it is true that it is not directly related to the clamp issue, but it's still worth talking about.

I also agree that most clamp capacitors retain a somewhat high voltage throughout the entire cycle. If they didnt, we'd loose a lot of energy there. I'd have to read it over again to be sure but that's the general case anyway. Normally a clamp capacitor charges up near the B+ level and stays there until a spike comes along and then the voltage rises as the capacitor absorbs the energy. After that the energy starts to dissipate through a bleeder resistance.
I'll try to read it again today sometime.

Flyback said:

I guarantee that the voltage across that cap is much above zero...when the fet is on, one side of the cap is zero volts, the other side is far below ground.

Click to expand...

You'd lose that bet. If both transistors are on during the switch time, how can the capacitor voltage be below ground??

the n and p fets are on alternately, not simulataneously

flyback might be right.
This makes me think that both FETs are only on during the 'cross over' time.
See full data sheet attached.

Flyback said:

the n and p fets are on alternately, not simulataneously

Click to expand...

To avoid a high voltage spike, the p-fet should be on slightly before the n-fet turns off, giving a slight overlap in their turn-off and turn-0n.

004 is the big N-FET. D-S
007 is the little P-FET. D-S

Here is the two gate voltages. Note the P-FET goes negative.

The LTSpice file takes about 5mS to get up and running. Don't even look at it for the first 4.5mS.