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Understanding SEPIC circuits

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Rusttree

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I've got a SEPIC circuit modeled in LTSpice and I'm trying to wrap my head around the theory. I put voltage probes on both inductors to see the behavior as the switch turns on and off. See the circuit attached and voltage graph. Green is L1, blue is L2, and magenta is the gate of the FET.

As the voltage at the inductor begins to rise when the switch turns off, it suddenly flat-lines after several microseconds. In my attached plot, the voltage at L1 flat-lines at about 6V and L2 flat-lines at about 3V. What's clamping the voltage from rising anymore?
 
Ok, I just got one step further. I plotted the current through the diode and realized the voltage clamps just as the diode begins conducting. So that answers that question. But now I'm confused by the diode's behavior. Why does it not conduct until the voltage has risen so high? Shouldn't it be conducting as soon as the voltage rises to the forward voltage bias of the diode?
 
Ah, because the cathode of the diode is not zero. Therefore, the voltage on the anode needs to rise to forward voltage bias above the cathode, which is why the diode doesn't conduct until the voltage has spiked high enough.

You know, I can stare at a problem for hours with no progress. But the minute I post something on a forum like this, it's epiphany city - even if no one has responded yet. There's gotta be some kind of psychological significance to that...
 
Ok, I just got one step further. I plotted the current through the diode and realized the voltage clamps just as the diode begins conducting. So that answers that question. But now I'm confused by the diode's behavior. Why does it not conduct until the voltage has risen so high? Shouldn't it be conducting as soon as the voltage rises to the forward voltage bias of the diode?

hi Russ,
Please post your LTSpice asc file, I will compare with what I see in simulation.

E.

EDIT;
Just seen your post #3.;)
 
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Explaining what you're asking often answers your question, happen to me often.
 
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