I've got a SEPIC circuit modeled in LTSpice and I'm trying to wrap my head around the theory. I put voltage probes on both inductors to see the behavior as the switch turns on and off. See the circuit attached and voltage graph. Green is L1, blue is L2, and magenta is the gate of the FET.
As the voltage at the inductor begins to rise when the switch turns off, it suddenly flat-lines after several microseconds. In my attached plot, the voltage at L1 flat-lines at about 6V and L2 flat-lines at about 3V. What's clamping the voltage from rising anymore?
As the voltage at the inductor begins to rise when the switch turns off, it suddenly flat-lines after several microseconds. In my attached plot, the voltage at L1 flat-lines at about 6V and L2 flat-lines at about 3V. What's clamping the voltage from rising anymore?