Using IC's?

[Electroenthusiast]

How many Logic IC's can i use in series (one after the other)?
Should i use a tri-state Buffer?
Does it depend on the Logic Family of the IC ?

 

[crutschow]

What do you mean by "in series", from one output to many inputs, or input to output to input?

 

[arunb]

you need to be more specific.

 

[pasanlaksiri]

What actually that you trying to do?

 

[Electroenthusiast]

one output to another input and so on for about 5-6 IC's...(Vcc=5V)
fan out?

 

[Hero999]

ICs should always be connected to the power supply in parallel, never in series.

 

[ericgibbs]

ICs should always be connected to the power supply in parallel, never in series.

hero,
He talking about 'fan out' for TTL not power rails.

 

[Hero999]

That's parallel, not series.

Well in that case it depends on the logic family and the frequency.

http://www.fisica.unlp.edu.ar/electro/computacion/downloads/Bibliografia/otros/IC_Logic_Families.pdf

 

[ericgibbs]

That's parallel, not series.

Well in that case it depends on the logic family and the frequency.

http://www.fisica.unlp.edu.ar/electro/computacion/downloads/Bibliografia/otros/IC_Logic_Families.pdf

As you dont normally connect ic outputs in parallel, it refers to the Inputs that are wired in parallel from a single output.

The number of combined inputs a single output can drive is called the Fan Out.

I didn't mention a series connection.???

 

[Hero999]

Thatr's what I meant.

The original poster mentioned a series connection.

 

[Electroenthusiast]

The number of combined inputs a single output can drive is called the Fan Out.

so how many ic can a IC drive?
Diode Drop in DL?

 

[Hero999]

Please post a schematic showing examples. It isn't clear what you mean.

 

[AlainB]

I am not an expert and I could easily be wrong but my understanding is that if each IC is having a Vcc and a ground connection, the answer to #1 and #5 should be infinite (in a perfect world).

#11 is not the same question anymore. There is a limit to the fan out (one output to many inputs). I read somwhere that the 74HC family can drive 50+ inputs but only 10 for the 74LS.

 

[crutschow]

Since a CMOS input draws no significant current, a CMOS output can drive a large number of CMOS inputs, limited primarily by how the capacitive loading from each input affects the desired operating speed.

A 74LS or other bipolar logic circuits require the output to sink current for a logic zero on each input. This typically limits the fanout to ten within a given logic family.

 

[audioguru]

He is not talking about "fan out".
Instead he is talking about one IC feeds a second IC that feeds a third IC that feeds a forth IC etc.
There is no problem except maybe the total delay might be too long if the final signal must coincide with a signal having the input timing.

 

[MikeMl]

Another typical thread started by r.vittalkiran. A vague question followed by twenty posts speculating what he/she was asking.

 

[ericgibbs]

He is not talking about "fan out".
Instead he is talking about one IC feeds a second IC that feeds a third IC that feeds a forth IC etc.
There is no problem except maybe the total delay might be too long if the final signal must coincide with a signal having the input timing.

one output to another input and so on for about 5-6 IC's...(Vcc=5V)
fan out?

This 'quote' was posted by the OP.

I would say fan out is what is being asked about, not serial connecting.

I would agree with MikeL's post, this OP frequently asks vague questions, perhaps we should insist he in future gives a clear description of his problem..

 

[atferrari]

It is amazing. So many good contributors in this forum, trying to reply questions that look like a troll every time.

Some serious questions have less luck in comparison.

I cannot believe he is serious in asking things like that.

 

[Electroenthusiast]

He is not talking about "fan out".
Instead he is talking about one IC feeds a second IC that feeds a third IC that feeds a forth IC etc.
There is no problem except maybe the total delay might be too long if the final signal must coincide with a signal having the input timing.

Thank You Everyone...


Sorry to annoyed ones, i had that doubt...

 

[ericgibbs]

Thank You Everyone...



Sorry to annoyed ones, i had that doubt...

hi,
I would suggest that you post a simple sketch diagram for future questions, in addition to the text description.