what do PIC and AVR mean

[JohnBrown]

The AVR isn't a simple copy of the PIC its a completely new archetecture designed to be a RISC processor. The PIC just happens to have a very small instruction set - its not a true RISC processor.

Surely RISC is an acronym for Reduced Instruction Set Computer?
So unless that means that you have to start with a large instruction set and then reduce it, like reducing a sauce or stock, then I'd say that the PIC qualifys as a RISC.
I don't think the term RISC had been coined when the first PICs were produced, whenever that was (I have a 1982 General Instruments data book featuring PICs from the pre-Microchip days).

Nigel, I think you'll find that the AVR is Harvard architecture, and the difference is not such much to do with keeping data and program memory separate as with having a separate bus for each, so that code and data can be accessed at the same time, avoiding what is often referred to as the Von Neumann bottleneck.

 

[bmcculla]

RISC does stand for Reduced Instruction Set Computer but the PIC was designed before RISC computers were defined like you said. There are properties about RISC Computers besides a small instruction set. One is uniform registers - all the registers are the same with no (or few) special purpose registers. Also RISC computers use few instructions to access memory just a load and store instruction and shouldn't have other instructions that access memory. Calling the PIC a RISC computer was a marketing decision to take advantage of the Buzz around RISC at the time.

PLLs Let you multiply input frequency. So you can have a cheap 10MHz crystal that gets multiplied up to 40MHz for the processor.

AVRs are faster(by 4 times). Which is useful but not critical, like Nigel said. It lets you ruduce the operating frequency which reduces EMI and power consumption.

There are differences in efficiency between instruction sets. Some processors have instructions that would take multipule instructions on other processors. This is one of the arguments for CISC. For example the 8051(CISC processor) has instructions to set or clear a single bit in memory which is very useful for control applications. On a risk processor you would have to read the Byte from memory change the correct bit and then load it back into memory - 3 instructions.

 

[Nigel Goodwin]

This is one of the arguments for CISC. For example the 8051(CISC processor) has instructions to set or clear a single bit in memory which is very useful for control applications. On a risk processor you would have to read the Byte from memory change the correct bit and then load it back into memory - 3 instructions.

As you are probably aware, the PIC has commands to directly set or clear a single bit, and to test a single bit - it's one of it's big advantages compared with most CISC processors.

You appear to be under some misconception what RISC means, as you already know it's 'Reduced Instruction Set' - reduced means less than previously, any processor which has less commands than it's predecessor can quite accurately be called RISC.

Certainly a mid-range PIC, with only 35 commands, falls well within the requirements for RISC.

 

[Noggin]

i mean does speed only depend on the instruction cycle. as i told u guys that i have been connected to the computer hardware industry for quite a long time. i have learnt from there that speed is not everything. its the architecture that has to be efficient. like AMD chips with lower clock frequencies compete with Intel chips working at higher clock frequencies. its because both of them have different architectures. so its not how fast a microprocessor works, its how efficiently it works!!!!! what are the advantages and disadvantages of the PIC and AVR architectures??

You are correct in noting that speed is not always top dog. The PIC if I'm not mistaken in saying so has very few instructions, even for a RISC. As someone pointed out one of the great things about a PIC is that you can set, test, or clear a bit in a single instructions (4 cycles) regardless of what the rest of the byte is. In an AVR you must read, set/test/clear, and then write. This takes 3 instructions (3 cycles) except for the test since you don't have to rewrite it.

In this case, the AVR is the winner... well, by clock cycles. You could definately go deeper into it by saying the 40 MHz PIC compared to the 16 MHz AVR the time difference in this situation is small.

whats the difference between a register to register architecture and an accumulator architecture. i have learnt that all microcontrollers use accumulator registers to store the results of operations e.g if we add A to B, the result C will be stored in an accumulator. so what is a register to register architecture.

Accumulator Architecture:
I believe the PIC does not have general purpose registers available and everything must be stored in memory locations, but note I am NOT familiar with the PIC so I could be mistaken!!!
Assume you have X stored in memory location [A]
Assume you have Y stored in memory location
Assume you want Z stored in memory location [C] and to be X + Y

load MEM(A) --- moves data in location A to the accumulator
add MEM(B) --- adds the data in location B to the accumulator
store MEM(C) --- stores the data in the accumulator to location C

12 cycles at 40 MHz = .3 uS

Register to Register architecture:
Best case scenario:
Assume X is in r16
Assume Y is in r17
Assume Z should be in r18

mov r16, r18 ---- moves the contents of r16 to r18, this is so that r16 isn't clobbered in the next step
add r18, r17 ----- addrs r17 to r18 and stores it in r18

2 cycles at 16 MHz = .125 uS

Worst case scenario is that I am processing data from an array in the dataspace somewhere and must use addressing things...

psuedo code:
load address into address pointer arrays X (two registers for this so 2 cycles)
load address into address pinter array Y (two registers again)
load address into address pointer array Z (again two registers)

load data in [X] to register and increment X (both can be done in 1 cycle)
load data in [Y] to register and increment Y
add data (don't care about clobbering data so one cycle)
store data in Z and increment register (one cycle)
test some condition
branch

In this case, the loading the address registers is insignificant compared to the processing of the array... assuming its a lot of data anyway. In this case we have 2 loads, 1 addition, 1 store, 1 test, and a branch. 6 cycles per addition...

6 cycles at 16 MHz = .375 uS

Even in this case with all the additional overhead of looping and array processing the AVR is coming out .075 uS per addition behind the PIC. I don't know how the PIC handles arrays, array indexing (incrementing possibly?) and all so I can't do a more detailed examination like this for that chip.

I do have a question though....

Are there any PICs that can compare to the higher end AVRs
128 kB flash
4 kB sram
4 kB EEPROM
2 USARTs
1 SPI
8 Channel 10 bit ADC
JTAG interface
2 16-bit timers
2 8-bit timers
1 two wire serial interface
1 analog comparator
8 external interrupts
self-programmable
watchdog timer
internal oscillator up to 8 MHz
53 IO pins
can operate at 2.7v (for 8MHz chips)

why is that so. actually im new to assembly. is it difficult to write programs for microcontrollers that use the accumulator architecture? what benefits does register to register architecture provide in writing programs using assembly.

I guess its really what you're used to. I started with writing for the x86 and AVR so thats what I'm comfortable with. If I was forced to write for a PIC I don't think I'd have a problem.... but reg to reg makes more logical sense to me.

 

[Nigel Goodwin]

I believe the PIC does not have general purpose registers available and everything must be stored in memory locations, but note I am NOT familiar with the PIC so I could be mistaken!!!

Just the opposite, a PIC has general purpose registers, and no extra memory!.

Assume you have X stored in memory location [A]
Assume you have Y stored in memory location
Assume you want Z stored in memory location [C] and to be X + Y

load MEM(A) --- moves data in location A to the accumulator
add MEM(B) --- adds the data in location B to the accumulator
store MEM(C) --- stores the data in the accumulator to location C

To do this on a mid-range PIC takes just two steps.

movfw A --- moves the contents of register A to the W register.
addwf B, f --- adds the contents of B to W, and stores the result in B.

If you want to store in in C, it would change slightly and add an extra step.

movfw A --- moves the contents of register A to the W register.
addwf B, w --- adds the contents of B to W, and stores the result in W.
movwf C --- move W to C.

Are there any PICs that can compare to the higher end AVRs
128 kB flash
4 kB sram
4 kB EEPROM
2 USARTs
1 SPI
8 Channel 10 bit ADC
JTAG interface
2 16-bit timers
2 8-bit timers
1 two wire serial interface
1 analog comparator
8 external interrupts
self-programmable
watchdog timer
internal oscillator up to 8 MHz
53 IO pins
can operate at 2.7v (for 8MHz chips)

I can't say I've ever really looked, I stick to mid-range PIC's, the spec above is hardly a micro-controller, more like a full blown micro-processor. Certainly the higher end PIC's have much higher specs than the low and mid range ones.

I've just had a quick look on MicroChip's site, with just a quick glance I noticed:

PIC18F8720
128KB program memory
3840 bytes RAM
1024 EEPROM
2 USARTS
1 SPI
MI2C
16 x 10 bit A2D
68 I/O pins
2 comparators
3 x 16 bit timer
2 x 8 bit timer
1 x wdt
25MHz clock speed

Pretty similar really?.

 

[samcheetah]

i thank all of you for such an informative experience for me.

i have some more question :lol:

from my evaluation,harvard architecture seems to be effiecient as opposed to the Von Neumann architecture. it is because data and program memory can be accessed at the same time. if im not mistaken the x86 processors are also of the von neumann architecture. but there the program and data memory is accessed simultaneously. if im wrong do tell me.

bmcculla said:

One is uniform registers - all the registers are the same with no (or few) special purpose registers

why should a RISC architecture need to have uniform registers. why do all of them have to be the same. why arent special purpose registers like flag registers worthy to be in a RISC processor.

AVRs are faster(by 4 times). Which is useful but not critical, like Nigel said. It lets you ruduce the operating frequency which reduces EMI and power consumption.

so that means that in a comparison between PICs and AVRs, the AVR stands out because of reduced EMI and low power consumption. but PICs dont work at very high frequencies (well below GHz) so why is this an issue. is EMI an issue at the frequencies on which the PIC works. and is power consumption an issue. or is it just a slight difference.

Nigel said:

As you are probably aware, the PIC has commands to directly set or clear a single bit, and to test a single bit - it's one of it's big advantages compared with most CISC processors

so a PIC is best of both the worlds i.e. its working is like a CISC processor and has a reduced instruction set like a RISC processor.


Noggin said:

As someone pointed out one of the great things about a PIC is that you can set, test, or clear a bit in a single instructions (4 cycles) regardless of what the rest of the byte is. In an AVR you must read, set/test/clear, and then write. This takes 3 instructions (3 cycles) except for the test since you don't have to rewrite it.

is this type of operation done quite frequently? i mean is this a determining factor?

Hey Noggin thanx for explaining the difference between accumulator architecture and register to register architecture. it will surely help me in the next semester when im going to study microcontrollers.

 

[bmcculla]

samcheetah:

Your right that the x86 is a von neumann(VN) processor. In a VN processor program and data memory is that same so you cant access it at the same time. The Pentium 4 looks like its doing this (instructions that the datasheet says take only one clock cycle) but from start to finish each instruction actualy takes about 30 clock cycles. The Pentium uses something called pipelining to push instructiuons though each clock cyce. Pipelining works like a bucket brigade - each of the 30 steps to execute an instruction take one clock but each of these steps can work at the same time with each instruction only one step behind. Like the bucket brigade it takes 30 steps to get a single bucket of wate to the fire but since each bucket is full as water is passed the water arrives every step.

The technical definition of RISC doesnt just mean reduced it also means simple (the opposite of Complex instrucion set CISC). Part of making it simple is the uniform registers it makes each instruction do things that are very similar. This makes a processor easy to pipleine.

The PIC insn't really a RISC processor thats why it has the instructions to set a single bit. The PIC really has a Reduced set of Complex instructions - not a true RISC processor. Theres nothing wrong with this - as Nigel pointed out it is actualy a benifit (one of the reasons CISC is good - each instruction can do more than the equivalent RISC instruction).

EMI is an issue even at lower frequencies. The clock desnt just generate the primary frequency; because its a square wave it also has higher multiples of that frequency which can cause interfreance.

Power consumption is usualy thought of in MIPS/mW or the number of instruction per power used. The faster the instructions goe through for a given power the better the MIPS/mW.

For control applications changing a single bit happens fairly often.

Sorry for being long winded
Brent

 

[samcheetah]

thanx bmcculla

oh yeah i remember the word pipelining and the prefetch process. one of the reasons for the AMD processor excelling the P4 in the beginning was the fact that the first core of the P4 (willamette) had too many stages in the pipeline. so there was some data prefetch error that degraded the efficiency of the process. but with the new core (northwood) and increasing clock frequencies the large number of stages are proving to be the winning factor for the P4 chips.

that bucket brigade analogy is kool. nice work.

The PIC insn't really a RISC processor thats why it has the instructions to set a single bit. The PIC really has a Reduced set of Complex instructions - not a true RISC processor. Theres nothing wrong with this - as Nigel pointed out it is actualy a benifit (one of the reasons CISC is good - each instruction can do more than the equivalent RISC instruction).

so that means that the PIC is an even better form of the RISC architecture.

EMI is an issue even at lower frequencies. The clock desnt just generate the primary frequency; because its a square wave it also has higher multiples of that frequency which can cause interfreance

thanx for pointing that out. i read that somewhere a few days ago that the harmonic frequencies of a square wave have higher multiples of the fundamental frequency. so this means that every microprocessor is prone to having problem with EMI and PIC isnt just the only one. even AVRs would have this problem. but which one stands out better in eliminating EMI? i think it is the AVR. am i right??

thanx again. i really appreciate the help.

 

[Nigel Goodwin]

thanx for pointing that out. i read that somewhere a few days ago that the harmonic frequencies of a square wave have higher multiples of the fundamental frequency. so this means that every microprocessor is prone to having problem with EMI and PIC isnt just the only one. even AVRs would have this problem. but which one stands out better in eliminating EMI? i think it is the AVR. am i right??

I wouldn't have thought there was much (if any) difference, however, it's directly related to clock speed - so the higher the clock, the more prone to EMI it will be. As AVR's can have higher clock speeds, they will probably produce more EMI? (at higher speeds).

However, I don't see as it's much of a problem, I've never heard of any EMI problems with PIC's - I would have thought the levels are extremely low - and AVR's will be similar.

 

[samcheetah]

so that sets the record straight in context to EMI generation for both PICs and AVRs.

 

[bmcculla]

EMI is related to clock speed - the faster the clock the more EMI (this is because as the frequency increaces the small traces on a PCB make better antennas). A PIC and AVR both running at 10 MHz should produce the same amount of EMI. Where ithe AVR has the advantage is that for the same 10MHz the AVR executes 4 times more instructions. So for the same amount of work you would only have to run the AVR at 2.5MHz. This does assume that the instruction sets are comparable; the fact that the AVR is a true RISC means that its instructions are a little simpler so it might take a little more (depending on the task) but the AVR does have more instructions so the two might offset each other.

 

[StupidDum]

I think power consumption is an issue.
Power consumption doesn't matter in DIY project. However, it is important in commercial product. It is annoying that you have to keep changing battery often.

 

[samcheetah]

I think power consumption is an issue.
Power consumption doesn't matter in DIY project. However, it is important in commercial product. It is annoying that you have to keep changing battery often

yes i do know that. but from what i have learnt i think that the power consumption of both PICs and AVRs are quite comparable. both PICs and AVRs consume very less power.so thats why i think power consumption is not an issue when compairing PICs and AVRs.

 

[StupidDum]

I think it is meaningless to argue about this.
I suppose most of the people here has not use AVR before, of course, including me.
From the conversation here, I also think those who use AVR has not use PIC before.

Come on, guys! Dont be emotional!
PIC or AVR is better? That is suppose to be Microchip and Atmel business, let them fight on that.
I dont really bother, if which microcontroller is proven to be better.. then I will consider to pick that.

 

[samcheetah]

StupidDum i agree with u. but by reading this thread i have learnt alot about microcontrollers.