Dick Cappels
Active Member
A little more detailed explanation of reduced Miller effect in cascodes: The lower transistor has the advantage of its collector driving the very low impedance of the emitter of the top transistor, thus the voltage gain is very small (much less than one), to the capacitive multiplying effects of the collector-to-base capacitance (aka Miller effect) is also very small. The top transistor has the benefit of its base being grounded, thus shunting most of the signal fed back through the collector-to-base junction to ground, similarly lowering the gain that causes the Miller effect.
At hundreds of MHz, parasitic reactances can make the performance of both transistors much less than ideal. Beware the SPICE simulation that dose not include strays and parasitics.
At hundreds of MHz, parasitic reactances can make the performance of both transistors much less than ideal. Beware the SPICE simulation that dose not include strays and parasitics.