The oscillators won't have exactly the same frequency, so their periods also won't be the same. Therefore when they are sync'd, their gated output will have the difference and cause a logic low when you don't want it.
The phase detector in a PLL will give an output (or invert it if you want) when their frequencies are close enough, regardless of their phase.
The phase detector in a PLL will give an output (or invert it if you want) when their frequencies are close enough, regardless of their phase.