Further thoughts on SPI for driving WS281x LEDs.
Summary: Using SPI to drive these LED is possible but there are issues that need to be addressed. I'm not convinced it's worth the effort.
The WS281x family of LEDs uses an odd timing based serial protocol.
The SPI clock rate has to match the WS device in a way that aligns with the WS 0 and 1 timings. An SPI clock period of 400 nS (2.5 MHz) would work if using 3 SPI bits to represent one WS bit. A WS 0 bit would looks like 400 nS high, 800 nS low (SPI bits would be 100). For a WS 1, it would be 800 nS high and 400 nS low (SPI bits are 110).
The SPI bits need to be packed into the 8 bit SPI buffer which then has to be loaded every 8 SPI clocks (3.2 uS). FIFO buffer SPI HW would be a big help. However, this discussion presumes the SPI HW just has a single byte buffer.
So that shows a stream of 9 bytes that must be fed to the SPI port at the correct time (approx every 8 SPI clocks, depending on the specific SPI HW). The WS serial engine does have some leeway as documented in the datasheet - about 300 nS max. However any longer delays in getting the byte to the SPI HW will cause the transfer to fail. This has implications for interrupts for simple SPI hardware. Either highest priority to the SPI int handler or ints off during the entire transfer sequence (and busy loop feeding the SPI port).
SPI clock: While I've shown a 2.5 MHz clock, there is some flexibility. The minimum high time for a 0 WS bit is 200 nS, maximum time is 500 nS. So a 2 Mhz clock might work though total time of a bit sequence would be slightly out of spec. The minimum low time for a 0 WS bit is 750 nS. Using the 3 bit encoding scheme from above, that makes the minimum SPI clock period 375 nS for a max clock rate of about 2.66 MHz. The timings for a 1 WS bit are reversed so we derive the same numbers. In summary, SPI clock range is 2 MHz to 2.66 MHz.[edit] Staying in spec, the clock range is 2.143 MHz to 2.667 MHz).[/edit] Note that the times mentioned above would have to be adjusted for a different clock rate.
The WS281x serial scheme makes it problematic to share SPI hardware. SPI devices all have an enable pin (CE, CS, Enable, ...) that prevent them from acting on random SPI signals. There is no such enable on the WS HW so it will respond to any signals on it's DI pin. This is undesirable as the WS will exhibit random behavior. So, either the SPI controller is dedicated to the WS LED string or a simple gate device is used. A single channel buffer with a enable pin would work though there are plenty of other devices. If driving the WS (a 5V device) from 3.3V or lower logic, the level shifter could incorporate an enable pin. I'm using a 74HCT buffer with output enable, for example. Note that any buffer device will need to be able to handle the data rate so take care in selecting a part for this.
There are alternate encoding schemes, 4 SPI bits per WS bit for example though they will require higher SPI clocks and faster response to filling the SPI buffer.