Hi,
i need to write a VHDL programme for my electronics course but don't have much knowledge in the subject.
need to write VHDL code that generates packets of binary data and displays them on a 7-seg display in hex. data includes 2 start bits which initialise the process. Only start bits 1-0 will be recognised. other start bits will be rejected until 1-0 is produced. Next comes a 4-bit header code which will be 1010. This bit of the specifies the receiver that the data will be sent to (always 1010). Next the channel bits. these are 2 bits that specify the channel the data is sent over. the channels are 0-0, 0-1, 1-0 or 1-1. Finally the data (4-bits) is sent over the channel. the data will actually be generated along with the channel so will be a 6-bit number. this number will be generated starting at 0-0-0-0-0-0 and increments by 1 on every negative clock edge.Once it reaches 1-1-1-1-1-1 it then repeats the cycle again. All data will then be sent to the display. the display has 4 7-seg displays.1st displays start code, 2nd header, 3rd channel, 4th data. all in hex. so 101010010011 will b 2A13
ANY help would be great, i'm just very lost...