I was incorrectly assuming the ESD protection design for I/O ports is the same as Input only. It now seems to be a well guarded secret how they make ESD protection. Some vendors are considering pnpn SCR clamps to Vss & Vdd as a low C solution for high speed logic, which will handle driver currents but make the device not function until power is recycled.
Also not all outsourced IC fabricators use the same ESD design, so it is important to verify all your assumptions. Also the design changes as lithography shrinks and devices get fast so the diodes must be faster and smaller too to limit pF of the diodes which affects input risetime.
We also assumed you know the max voltage rating for resistors.
If the resistor is connected to the grid, you better not rely on one 250V rated R when 3kV transients ought to be expected.
Yety Microchip assume you understand this. But they do understand the current limit is protected by the internal dual stage ESD protection. High means 110 rms 60Hz and 162Vpk
i.e. DO NOT DO THIS with one 1/4W resistor rated for 250V
http://ww1.microchip.com/downloads/en/AppNotes/00521c.pdf
p1
Don't confuse system level ESD tests with high current compared to human body model (HBM) 100pF tests for IC protection.
Microchip says ...
Although most silicon is warranted to survive some level of contact with ESD HBM peak currents, they generally are not warranted to survive 5.5x higher IEC 61000-4-2 peak surge currents without external ESD protection logic. The ratings that are used for protecting ICs in the manufacturing environment, such as HBM and CDM, are not equivalent to system level ESD tests in IEC 61000-4-2)
What happens with latchup?
Well with 18V CD4xxx series the chip gets hot but due to high resistance usually survives, but with lower voltage devices like 5.5V 74HC and 3.6V 74ALC family the RdsOn is now reduced to 50 and < 25 ohms respectively, so the chip is more likely to silently "burn" out a weak link and you may smell epoxy but no outer visible signs.