Is it possible to eliminate hold time? (Flip-Flop)

[electroRF]

Hi,
I ran into this interview question which stated: how to eliminate the hold time? (Flip Flop related - Hold Time is the time that the input is required to remain stable after the clock (rising) edge)

I wonder how is that possible?

I guess that they'd expect some creativity.

Thank you for any feedback!

 

[user_88]

Are you talking about propagation delay? I think that is just an inherent property of the flip flop. There wouldn't be anything you could do ... in a practical sense ... to change it.

 

[KeepItSimpleStupid]

"hold time"

A flip flop holds its state until it is changed or the power gets turned off. So, don;t turn the power off and it's infinite.

Basically I have no idea what they are talking about. Are they talking about how long the inputs have to be stable?

 

[MikeMl]

Most flip-flops and latches have a Hold time spec. It is the time the J,K,T, of D input has to be stable after the sampling edge of the clock input. Some flops have a negative Hold time, meaning that the input can change slightly before the clock edge and the previous state of the input will be sampled...

Hanging a capacitor on said input(s) would go a long way in reducing a positive Hold time to zero or making it negative.

 

[Electroenthusiast]

The OP has not phrased the question properly. Please be clear. I did not get what you mean by 'eliminating' hold time.
Consider a SR Latch/Flip Flop, if S and R is 0,0. The preceding state of the output continues.

 

[KeepItSimpleStupid]

Here https://www.google.com/url?sa=t&rct...MBRuyV1sV_eH_dJzM62qdLQ&bvm=bv.55819444,d.cWc is a datasheet for an SR FF.

Hold time isn't listed

Minimum Set-up time is.

 

[MikeMl]

Here https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=3&ved=0CDUQFjAC&url=https://www.fairchildsemi.com/ds/CD/CD4013BC.pdf&ei=fZN0UsOWFOexsAS144CIBQ&usg=AFQjCNGhfhGMBRuyV1sV_eH_dJzM62qdLQ&bvm=bv.55819444,d.cWc is a datasheet for an SR FF.

Hold time isn't listed
Minimum Set-up time is.

OTOH, it is listed on this data sheet.

 

[electroRF]

Hi mates.
Thank you very much!

To clarify the question (I'll also edit it), I meant how to have the FF not requiring for the input to remain stable a certain time (called hold time) after the clock's (rising) edge.

Mike:

Most flip-flops and latches have a Hold time spec. It is the time the J,K,T, of D input has to be stable after the sampling edge of the clock input. Some flops have a negative Hold time, meaning that the input can change slightly before the clock edge and the previous state of the input will be sampled...

Hanging a capacitor on said input(s) would go a long way in reducing a positive Hold time to zero or making it negative.

That sounds great.

Though it may increase the setup time of the FF, right?
As you add capacitance to the input stage, and therefore need more time to charge it.

 

[ronsimpson]

TI 74hct74 DFF.
Data must be stable 17nS before the rising edge of Clock and Data must be stable 0nS after the rising edge of Clock.
Data setup=17 Data hold=0

Lets day that your data arrives 1uS be clock but the data changes 3nS before the clock. So you need a data hold of -3nS.
74hct14 delay 20nS
DATA----------------------------D
CLOCK----Invert----Invert----C (added 40nS of delay to the clock)
Note the data needs to be stable 57nS before clock and can change 40nS before clock.
We just made a DFF with a setup time of 57nS and a hold time if -40nS.

Delay the clock, and the hold time is changed. (can use a small resistor capacitor delay on the clock input) In 74HCxx and CD4xxx logic it is common to find RCs on the board to delay signals. In 74LS the resistors need to be small in value, 220 ohms or less while in cmos the resistors can be up to mega ohms.

 

[MikeMl]

...
Though it may increase the setup time of the FF, right?
As you add capacitance to the input stage, and therefore need more time to charge it.

Right on.

 

[narasimhan]

TI 74hct74 DFF.
Data must be stable 17nS before the rising edge of Clock and Data must be stable 0nS after the rising edge of Clock.
Data setup=17 Data hold=0

Lets day that your data arrives 1uS be clock but the data changes 3nS before the clock. So you need a data hold of -3nS.
74hct14 delay 20nS
DATA----------------------------D
CLOCK----Invert----Invert----C (added 40nS of delay to the clock)
Note the data needs to be stable 57nS before clock and can change 40nS before clock.
We just made a DFF with a setup time of 57nS and a hold time if -40nS.

Delay the clock, and the hold time is changed. (can use a small resistor capacitor delay on the clock input) In 74HCxx and CD4xxx logic it is common to find RCs on the board to delay signals. In 74LS the resistors need to be small in value, 220 ohms or less while in cmos the resistors can be up to mega ohms.

Nice example. But I think it needs a bit of clarification. I think the circuit should have been like
DATA------Invert----Invert----D (added 40nS of delay to the Data)
CLOCK--------------------------C
This gives negative hold time and positive setup time for the circuit(which includes the FF and the 2 inverters) between CLOCK and DATA.
Or in simple words. Since the DATA changes 3ns before clock which is not to our liking(We want the flipflop to process the data before this change) we delay it by some time so that the data changes well after the clock and that change is not reflected in the flipflop.
It is like a running race. DATA finishes(arrives) 3ns before CLOCK. There are 2 ways to rectify this. Either delay DATA or make CLOCK faster(reduce delay between CLOCK and C). In real time circuits we only have delay elements.
I gave the above clarification based on my understanding of the problem. I might have incorrectly interpreted it.
If the intention was to make the Flipflop process the new data(ie the value of DATA after the change(3ns)) then the circuit given by ronsimpson is correct but still that will give positive hold time and negative setup time for the circuit(which includes the FF and the 2 inverters) between CLOCK and DATA.
Some of my friends do not like the concept of negative hold time and negative setup time(especially -ve setup time). A flipflop as such cannot have -ve setup time. But the circuit as such can have if the clock is delayed as above.

 

[electroRF]

Hi Ron and NaraSimhan,

Thank you very much!

Nara, first of all, welcome to the forums! I see that it's your first post here

I think that Nara is right - for having negative Hold Time, you need to delay the DATA, and not the Clock.

Delaying the Clock will make the hold time become positive.

There are 2 ways to rectify this. Either delay DATA or make CLOCK faster(reduce delay between CLOCK and C)

Is increasing the Clock Frequency an option for making the clock faster?

 

[ericgibbs]

hi RF,
By Delay the Data, do you mean Hold the Data until the active Clock edge has reached its steady state?
E

 

[electroRF]

By Delay the data, i mean to add delay to the data path between the source and the FF's Data Entry.

if you add 40ns delay to the data Path, in relation to the Clock Path (assuming there was no delay difference between their paths before this addition), that means that:
if the FF Setup Time is 17sec, then the Data needs to be stable 57sec before clock
If the FF Hold time is 0sec, then the data needs to remain stable up to 40sec before the clock changes.

Did that answer your question?

 

[ericgibbs]

Did that answer your question?

hi RF,
It was not really question about the actual times, it was asking what you meant by delay.
A Delay could mean holding off an Event or holding on a State

 

[MrAl]

Hello there,

Setup time refers to the state of the data before the clock, Hold time refers to the state of the data after the clock.

Using a capacitor directly with digital logic in the data or clock path is not a recommended practice although it has been done. Basically a capacitor is an analog device and a digital logic gate is a digital device and they have to be treated as different species. The capacitor could very well change the setup time as well as the hold time, and more importantly, it causes an analog signal to be developed at the input of a digital logic element...something that should definitely be avoided.

The exception is when using a specialized gate such as a Schmitt Trigger. In this case, we can construct an asymmetrical delay element using for example a resistor, capacitor, open connector gate, and Schmitt Trigger inverter. This would delay or stretch one edge of the data but not the other. To degeneralize a little, say we have a data signal that goes high before the clock and goes low later, and we want it to hold high longer. In this case we would want to stretch the pulse out so that the falling edge happens a little later than the actual signal falling edge but we want to leave the rising edge alone. This small circuit would be built using the above mentioned parts, and is very similar to a MOSFET asymmetrical drive circuit.

Of course it is also possible to simply use another flip flop ahead of the one in question and control the output state accordingly, but the pulse stretcher above is probably the simpler solution. That kind of circuit has actually been used in some consumer and government equipment. If you'd like to see a schematic i can supply one.

 

[narasimhan]

Hi Ron and NaraSimhan,

Thank you very much!
Nara, first of all, welcome to the forums! I see that it's your first post here
I think that Nara is right - for having negative Hold Time, you need to delay the DATA, and not the Clock.
Delaying the Clock will make the hold time become positive.
Is increasing the Clock Frequency an option for making the clock faster?

Thanks. Actually I dont remember signing up for this site. It says I've been a member for 5 yrs. I tried signing up yesterday(to post a reply here) and it said the email already exists so I came to know that I'm a member(actually quite senior member taking the 5 yrs into account).
Increasing the clock frequency without changing the hold/setup time will not improve things. If say in the above circuit example clock period is 100ns(freq 10 MHz). If you increase frequency to say 20MHz(period 50ns) and if you don't improve on the setup time then the circuit will still behave the same.

hi RF,
It was not really question about the actual times, it was asking what you meant by delay.
A Delay could mean holding off an Event or holding on a State

Delay hear means just adding a buffer(or 2 inverters). Here is a crude example

You can interpret it whatever way you want. But remember it delays the entire input signal(it does not alter or stretch the signal). If you want some portion of the input signal to get delayed(that is you want some part of input to kindof expand then you need to use the schmit trigger kind of circuit(posted above)). But that alters the waveform which may not be the intention unless you want to be partial to some values of input.