I came to the same conclusion, a positive edge triggered D flip flop, with the clock input tied to one input on a AND gate, and the Q output going to the second input on the AND gate. The change of 0->1 at the clock will only carry through the to the final output if D is also 1 at the instant of 0->1 on the clock. If D is 0 at the instant of clock 0->1, Q will be set (or remain) at 0, and the AND gate will output 0.
The negative edge triggered D flip flop however, I don't think will work. If the clock is 0 at any moment, I must be positive the final output is also 0. If clock drops from 1 to 0, while D is 1, that will set Q as 1, which I don't want.
Now I'm having a tough time finding a IC with at least 6 D flip flops, with seperate clocks, and if possible, a common data.
The purpose of this is a fuel injector pulse interrupt, where it will kill a entire pulse only, never able to make a partial pulse. The number of skipped events will be a result of the duty cycle of a PWM signal on the data inputs. 100% duty, all pulses get thruogh, 75% duty, only 75% of the pulses get through. I understand it will be a hit and miss strategy, like flipping a coin, but with 100s of pulses a second, it will balance out. The law of large numbers I think.
I'm probably also going to have two frequency to voltage converters, one for a front wheel speed detector, the other for a rear wheel speed detector, and a voltage comparator of those two outputs. More voltage, more speed disparity, and inferred wheel spin. This voltage will then go into a inverse voltage to PWM conversion (0V=100% duty, more voltage is less duty), which will be fed to the data inputs on all the above flip flops. End result, high speed, electronic, fuel based traction control.