Here's the schematic as advertised. It's not ideal, but could be a starting point for someone with the necessary skills to interpret it and build a prototype circuit from it, if they wish. I deliberately have not included such details as IC pin-outs, D/A details and construction, because of safety concerns: if you can't work from the schematic your skill level may not be enough to build this safely and you should refer it to a competent technician locally. If built, the circuit should be subjected to thorough bench-testing without a motor connected.
For image clarity reasons I have posted the schematic in two parts. Stage 1 drives stage 2.
Operation
In stage 1 four ground-referenced switches In1-In4 selectively control transmission gates U2a-d via inverters U1a-d. Transients/interference on the switch leads are suppressed by TVS devices TVS1-4, chokes L1-4 and capacitors C1-4.
A clock oscillator is formed by R5, C5 and Schmitt inverter Uie, with feedback via whichever transmission gate is open (conductive) and via Pot1 or Pot2 as appropriate. R5 sets the minimum oscillation period at ~1mS.
The oscillator output clocks both a 12-stage counter U4 and a decade counter U5. U4's Q10 output pulses at ~1Hz (if double or half that were to prove useful then the Q9 or Q11 output could be selected instead by a jumper or switch).
Each Q10 pulse resets (via C7, R7) counter U5, which proceeds to count the 1mS clock pulses. When a preset count (1-9) is reached (determined by jumper selection of a suitable output of U5) the U5 clock input is disabled. NAND gtes U3b, U3c enable the preset number of 1mS pulses to pass to the next stage. R6/C6 slightly delay the clock pulses into U3c to overcome a glitch due to inherent IC response time.
U3a gives an up/down count control signal for the second stage.
In the second stage U7/U8 together form an 8-bit counter clocked by the gated 1mS pulses from the first stage. An 8-bit D/A converter provides an analogue output from the counter value. The Up/down signal from stage 1 determines the count direction.
To prevent count wrap-around, U9 detects if all 8 bits are '1' when counting up, and U10a,b detect a count of zero when counting down. Either detected event disables further counting via gate U6a.
A power-on reset function for U7/U8 ensures the count starts at the '4mA count'.
R10/R11 scale the D/A converter output to a value used as a reference for a comparator formed by op-amp U13. U13 controls the current through R13, hence through the control loop, so that the voltage dropped across R13 equals the reference.
[Simulation files are attached, but need model files CD4000.lib, CD4066.sub, potentiometer.sub, LM324NS.mod to run]