Hi everyone
I need to generate the pattern across the portB -mentioned in the look up table at 67Khz frequency.
With the below when montired in the oscillscope - the frequecy was hardly 100Hz. Do i need to add more delay or increase the counter value to get the pattern generated at 67Khz frequency.
Can anyone help me on this??
-
LIST p=16F876A ;tell assembler what chip we are using
include "P16F876A.inc" ;include the defaults for the chip
;----------------------
#define CONF1 _CP_OFF & _DEBUG_OFF & _CPD_OFF
#define CONF2 _LVP_OFF & _BODEN_OFF & _PWRTE_ON & _WDT_OFF & _HS_OSC
__CONFIG CONF1 & CONF2
;---------------------
cblock 0x20 ;start of general purpose registers
count ;used in table read routine
count1 ;used in delay routine
counta ;used in delay routine
countb ;used in delay routine
endc
;-------------------------
LEDTRIS Equ TRISB ;set constant for TRIS register
;---------------------------
org 0x0000 ;org sets the origin, 0x0000 for the 16F876A
;-----------
;this is where the program starts running
movlw 0x07
movwf CMCON ;turn comparators off (make it like a 16F876)
bsf STATUS, RP0 ;select bank 1
movlw b'00000000' ;set PortB all outputs
movwf LEDTRIS
bcf STATUS, RP0 ;select bank 0
;------------------
Start clrf count ;set counter register to zero
Read movf count, w ;put counter value in W
call Table
call Delay
incf count, w
xorlw d'14' ;check for last (14th) entry
btfsc STATUS, Z
goto Start ;if start from beginning
incf count, f ;else do next
goto Read
Table ADDWF PCL, f ;data table for bit pattern
retlw b'00000000'
retlw b'10000010'
retlw b'10000011'
retlw b'10000010'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'00110100'
retlw b'00110001'
retlw b'01100000'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'10000010'
retlw b'10000011'
retlw b'00000000'
retlw b'10000010'
Delay movlw d'2' ;delay 250 ms (4 MHz clock)
movwf count1
d1 movlw 0xC0
movwf counta
movlw 0x01
movwf countb
Delay_0
decfsz counta, f
goto $+1
decfsz countb, f
goto Delay_0
decfsz count1 ,f
goto d1
retlw 0x00
;------------------------------
end
I need to generate the pattern across the portB -mentioned in the look up table at 67Khz frequency.
With the below when montired in the oscillscope - the frequecy was hardly 100Hz. Do i need to add more delay or increase the counter value to get the pattern generated at 67Khz frequency.
Can anyone help me on this??
-
LIST p=16F876A ;tell assembler what chip we are using
include "P16F876A.inc" ;include the defaults for the chip
;----------------------
#define CONF1 _CP_OFF & _DEBUG_OFF & _CPD_OFF
#define CONF2 _LVP_OFF & _BODEN_OFF & _PWRTE_ON & _WDT_OFF & _HS_OSC
__CONFIG CONF1 & CONF2
;---------------------
cblock 0x20 ;start of general purpose registers
count ;used in table read routine
count1 ;used in delay routine
counta ;used in delay routine
countb ;used in delay routine
endc
;-------------------------
LEDTRIS Equ TRISB ;set constant for TRIS register
;---------------------------
org 0x0000 ;org sets the origin, 0x0000 for the 16F876A
;-----------
;this is where the program starts running
movlw 0x07
movwf CMCON ;turn comparators off (make it like a 16F876)
bsf STATUS, RP0 ;select bank 1
movlw b'00000000' ;set PortB all outputs
movwf LEDTRIS
bcf STATUS, RP0 ;select bank 0
;------------------
Start clrf count ;set counter register to zero
Read movf count, w ;put counter value in W
call Table
call Delay
incf count, w
xorlw d'14' ;check for last (14th) entry
btfsc STATUS, Z
goto Start ;if start from beginning
incf count, f ;else do next
goto Read
Table ADDWF PCL, f ;data table for bit pattern
retlw b'00000000'
retlw b'10000010'
retlw b'10000011'
retlw b'10000010'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'00110100'
retlw b'00110001'
retlw b'01100000'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'00000000'
retlw b'10000010'
retlw b'10000011'
retlw b'00000000'
retlw b'10000010'
Delay movlw d'2' ;delay 250 ms (4 MHz clock)
movwf count1
d1 movlw 0xC0
movwf counta
movlw 0x01
movwf countb
Delay_0
decfsz counta, f
goto $+1
decfsz countb, f
goto Delay_0
decfsz count1 ,f
goto d1
retlw 0x00
;------------------------------
end