According to the schematic, the drain of Q1 is connected directly to the gate of Q3. But you show Q1 drain at zero volts and Q3 gate at 8.5 volts.
Something isn't right there.
And, if SW3 is closed, it is hard to see how the gate of Q1 could be at 7.4 volts. SW3 should connect it directly to ground. Are you sure SW3 is closed?
Likewise, it is hard to see how the gate of Q2 could be at zero volts if SW2 is open. Are you sure SW2 is open?
According to the schematic, the drain of Q1 is connected directly to the gate of Q3. But you show Q1 drain at zero volts and Q3 gate at 8.5 volts.
Something isn't right there.
And, if SW3 is closed, it is hard to see how the gate of Q1 could be at 7.4 volts. SW3 should connect it directly to ground. Are you sure SW3 is closed?
Likewise, it is hard to see how the gate of Q2 could be at zero volts if SW2 is open. Are you sure SW2 is open?
You may have to take any measurement referring the DMM black lead (COM) to the source pins of Q1 and Q3 ( you marked 0V )on the schematic.
the set of readings should refer to various logical states of sw1, sw2 and sw3. Naturally there would be 9 different states . Even if we are not interested in the cases where SW1 is OFF, there would be 4 states. For all the 4 states, we need the voltages t Gate and drain of Q1 and Q3 and Gate,Drain and Source of Q2.
results appear absurd in the sense, Q3 source can never get any voltage as it is at 0V line always.