hello everyone.... i need a help on the following code. first i will explain the whole problem. it is as below
i need to transfer data from a master to a slave. am doin the interconnect part of it. my master and slave supports 32 bit data n address bus. so at a time i can transmit upto 4 bytes of data. any data which is more than that need to be transmitted more than once. my protocol supports burst transfer. it can transmit upto 128 bytes of data 16 times ie is the size and length respectively. am using the folowing algoritghm...
value <= (size/4) -- since i can transmit only 4 bytes a time
for( i = 0 ; i < length ; i++)
{
for( j = 0 ; j < value ; j++)
{
addr <= data ;]
addr <= addr + 4;
}
addr <= addr+ length;
}
how can this be implemnted in vhdl. am trying this for many weeks. i couldnt find how to proceed. also how can i show the out put. am using xilinx 6.1 and modelsim 5.5... please help me on this. i have written the code like this
for j in 1 to len loop
for i in 1 to value loop
addr <= data;
addr <= addr + 4;
end loop;
addr <= addr + len;
end loop;
it says ' + ' cannot be used in that context. am unable to show the out put also. tell me what should i declare addr and data as. i want to see the transition after every 4 bytes of data is transimtted.
i want to see the out put like this.. here length = 2 and size = 16bytes
.........____ ______ _____ _____ ____ ______ ______ ______
data <_1__><__2__><__3__ ><__4___><__1__><__2__><__3__ ><__4___>
please help me...
thanking you...
with great regards...
i need to transfer data from a master to a slave. am doin the interconnect part of it. my master and slave supports 32 bit data n address bus. so at a time i can transmit upto 4 bytes of data. any data which is more than that need to be transmitted more than once. my protocol supports burst transfer. it can transmit upto 128 bytes of data 16 times ie is the size and length respectively. am using the folowing algoritghm...
value <= (size/4) -- since i can transmit only 4 bytes a time
for( i = 0 ; i < length ; i++)
{
for( j = 0 ; j < value ; j++)
{
addr <= data ;]
addr <= addr + 4;
}
addr <= addr+ length;
}
how can this be implemnted in vhdl. am trying this for many weeks. i couldnt find how to proceed. also how can i show the out put. am using xilinx 6.1 and modelsim 5.5... please help me on this. i have written the code like this
for j in 1 to len loop
for i in 1 to value loop
addr <= data;
addr <= addr + 4;
end loop;
addr <= addr + len;
end loop;
it says ' + ' cannot be used in that context. am unable to show the out put also. tell me what should i declare addr and data as. i want to see the transition after every 4 bytes of data is transimtted.
i want to see the out put like this.. here length = 2 and size = 16bytes
.........____ ______ _____ _____ ____ ______ ______ ______
data <_1__><__2__><__3__ ><__4___><__1__><__2__><__3__ ><__4___>
please help me...
thanking you...
with great regards...