I have a D type flip flop that I want to reset about 4nsec after the Q output goes high (sort of a 'one shot' circuit). Could someone give me a reliable circuit for that. The reset is active high and the flip flop comes with complementary outputs.
Thanks David; so the 4 nsec time in the unstable state can be set with this RC; but through what path the capacitor will discharge back to zero volts so that the D flip flop is ready for the data at next clock cycle.
First of all the 4ns is a very short pulse, you must use a fast response time logic if you want a cvasi-rectangular pulse. For example the HC series have 6-8ns rise/fall time and this series is faster than LS-TTL so you must use AC series with 2-3ns rise/fall time. In this cases simply use propagation delay through circuits to generate such short pulses.