Hello, I am designing motherboard for AMD AM486 processor.
Processor works on 120Mhz, 3x40Mhz with CLKMUL.
Problem is to design clock sqwave signal 40Mhz which will be decreased to 5Mhz for parallel transfer while 40Mhz will be used for serial.
I'm also wondering will processor wait for slower frequency to deliver data without external activation of HOLD pins because I am not using any chips to control processor HW interrupts.
I don't have any instruments to test on, so every advice is welcome.
Here is my starting scheme and I don't expect it to be correct:
quartz oscillator (Q1):[ COF-50 40Mhz, 5V, AEC 10k, 4 pins(with 1 NC pin) ]
Processor works on 120Mhz, 3x40Mhz with CLKMUL.
Problem is to design clock sqwave signal 40Mhz which will be decreased to 5Mhz for parallel transfer while 40Mhz will be used for serial.
I'm also wondering will processor wait for slower frequency to deliver data without external activation of HOLD pins because I am not using any chips to control processor HW interrupts.
I don't have any instruments to test on, so every advice is welcome.
Here is my starting scheme and I don't expect it to be correct:
quartz oscillator (Q1):[ COF-50 40Mhz, 5V, AEC 10k, 4 pins(with 1 NC pin) ]
