undervoltage design

Rsw controls the turn on time of the FET and limits the current from the op amp. For example if your FET has a total gate charge of 10 it would have a turn on time of about 12.5 usec. It looks to me that the 1495 can drive more current than the 5 meg would require so I would make it smaller--but that's just me. Don't forget it needs to be a logic level FET.
 
I have another question regarding this circuit. If i want to change high side pmos switch to low side nmos switch what changes i hav to make in circuit and design?
 
I also didnt understand the Hysterisis equation. Can anybody please explain how hysterisis has been calculated
 
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