Ok
I pulled some of the stats from the manual, and as far as speed wise, it says here that my controller has a programmable freq rnge of 12-25, I cannot find anywhere in the manual where it says that my channel runs @ 1.5. It does say that it supports full speed usb though.... Is that a good thing?? lol...
I'm so damn persistant with these things, because I'm just the type of guy that has to make things work!!!!!!!!!!!!!!!! ahhha
when there not the way I want them to... Close to impossible mabee..... But somebody has to be Ethen Hunt right? anyways. I also looked at the controller you were talking about and I was reading up on it it said that only one channel could be set to 24/96 because of the limits of 12/mbps, and it could handle only 1 input or output of that resolution.... It also went on to say that if you were going to use it for multichannels that the resolution would have to be set @ 16bit 44.8 or 48mhz... If I was reading it right..... I also could only find an adobe file on the controller, when I went to the actual site it said that the domain was for sale?? wtf? I don't know.... Anyways if you could give me you opinon based on the information I have provided that would be frakin AwsomE!!!
Thanks!
I mean if it says it has a programmable range of 12-25 that means that the 6mhz crystal generates the signal for the controller and since the controller has an onboard oscillator, it takes that signal and boosts it to 12??
is that right? so it does run @ 12? Or am I totatlly lost?
A block diagram of the adaptive clock generator is shown in Figure 2–1. The frequency synthesizer circuit generates
a programmable clock with a frequency range of 12–25 MHz. The output of the frequency synthesizer feeds the
divide-by-M circuit, which can be programmed to divide by 1 to 16. As a result, the frequency range of the MCLKO
signal is 750 kHz to 25 MHz. The duty cycle of the MCLKO signal is 50% for all programmable MCLKO frequencies.
Clock Generation
The TUSB3200 requires an external 6-MHz crystal and PLL loop filter components connected as shown in Figure 4-1
to derive all the clocks needed for both USB and CODEC operation. Using the low frequency 6-MHz crystal and
generating the required higher frequency clocks internal to the IC is a major advantage regarding EMI.
The USB interface includes an integrated transceiver that supports 12 Mb/s (full speed) data transfers. In addition
to the USB control endpoint, support is provided for up to seven in endpoints and seven out endpoints. The USB
endpoints are fully configurable by the MCU application code using a set of endpoint configuration blocks that reside
in on-chip RAM. All USB data transfer types are supported.
An on-chip phase lock loop (PLL) and adaptive clock generator (ACG) provide support for the USB synchronization
modes, which include asynchronous, synchronous and adaptive.
Universal Serial Bus (USB)
• USB Specification version 1.1 compatible
• USB Audio Class Specification 1.0 compatible
• Integrated USB transceiver
• Supports 12 Mb/s data rate (full speed)
• Supports suspend/resume and remote wake-up
• Supports control, interrupt, bulk and isochronous data transfer types
• Supports up to a total of 7 in endpoints and 7 out endpoints in addition to the control endpoint
• Data transfer type, data buffer size, single or double buffering is programmable for each Endpoint
• On-Chip adaptive clock generator (ACG) supports asynchronous, synchronous and adaptive
synchronization modes for isochronous endpoints
• To support synchronization for streaming USB audio data, the ACG can be used to generate the master
clock for the CODEC
• Configurable to support AC’97 1.X, AC’97 2.X or I2S serial interface formats
• I2S modes can support a combination of up to 4 DACs and/or 3 ADCs
• Can be configured as a general-purpose serial interface
• I2C Interface
• Master only interface
• Does not support a multimaster bus environment
• Programmable to 100 kbit/s or 400 kbit/s data transfer speeds
• Pulse Width Modulation (PWM) Output
• Programmable frequency range from 732.4 Hz to 93.75 kHz
• Programmable duty cycle
• General Characteristics
• Available in a 52-Pin TQFP Package
• On-chip phase-locked loop (PLL) with internal oscillator is used to generate internal clocks from a 6 MHz
crystal input
• 3.3-V core and 5-V compatible input/output buffers used for CODEC port interface
• Reset output available which is asserted for both system and USB reset
• External MCU mode supports application firmware development
The TUSB3200 device supports all the USB data transfer types, which are control, bulk, interrupt, and isochronous.
In accordance with the USB specification, endpoint zero is reserved for the control endpoint and is bidirectional. In
addition to the control endpoint, the TUSB3200 is capable of supporting up to 7 in endpoints and 7 out endpoints.
These additional endpoints can be configured as bulk, interrupt, or isochronous endpoints. The MCU handles all
control, bulk, and interrupt endpoint transactions. In addition the MCU can handle isochronous endpoint transactions,
such as a rate feedback endpoint to the host PC. However, for streaming isochronous data between the host PC and
the CODEC interface port, the DMA channels are provided.
Isochronous Out Transaction (host PC as source and CODEC as destination)
The steps to be followed for an isochronous out transaction are as follows:
1. MCU initializes one of the out endpoints as an out isochronous endpoint by programming the appropriate
USB endpoint configuration block. This entails programming the buffer size and the buffer base address
for both the X and Y buffers and the bytes per sample bits, setting the isochronous endpoint bit, enabling
the endpoint, and clearing the NACK bit.
2. The MCU initializes one of the four DMA channels to support the isochronous out endpoint by programming
the appropriate DMA configuration registers.
3. The host PC sends an out token packet followed by a data packet addressed to the out endpoint. The UBM
writes the data packet to the X (or Y) endpoint buffer, updates the sample count in the data count byte, and
sets the X (or Y) buffer NACK bit to a 1. Note that the number of audio samples and not the number of bytes
is written to the data count byte. Also, note that there is no endpoint interrupt generated for isochronous
endpoints. If a buffer overflow occurs, the UBM will set the overflow bit in the endpoint configuration byte.
4. The DMA channel reads the X (or Y) buffer data count byte to verify that the NACK bit is set and to obtain
the sample count in the new data packet. The DMA channel then clears the NACK bit and streams the data
to the CODEC port interface. Note that if a new data packet has not been received, the NACK bit will not
be set, and the DMA channel will not move any data to the CODEC port interface.
2.2.7.4.2 Isochronous Out Transaction (host PC as source and MCU as destination)
The steps to be followed for an isochronous out transaction are as follows:
1. MCU initializes one of the out endpoints as an out isochronous endpoint by programming the appropriate
USB endpoint configuration block. This entails programming the buffer size and the buffer base address
for both the X and Y buffers and the bytes per sample bits, setting the isochronous endpoint bit, enabling
the endpoint, and clearing the NACK bit.
2. The host PC sends an out token packet followed by a data packet addressed to the out endpoint. The UBM
writes the data packet to the X (or Y) endpoint buffer, updates the sample count in the data count byte, and
sets the X (or Y) buffer NACK bit to a 1. Note that the number of audio samples and not the number of bytes
is written to the data count byte. Also, note that there is not an endpoint interrupt generated for isochronous
endpoints. If a buffer overflow occurs, the UBM will set the overflow bit in the endpoint configuration byte.
3. After an SOF or PSOF interrupt, the MCU reads the USB frame number register and uses the least
significant bit (bit 0) value as the buffer select bit. If bit 0 is a 0 for the current USB frame, then the MCU should
access the Y buffer. If bit 0 is a 1 for the current USB frame, then the MCU should access the X buffer.
2–14
4. The MCU reads the X (or Y) buffer data count byte to verify that the NACK bit is set and to obtain the sample
count in the new data packet. Note that if a new data packet has not been received, the NACK bit will not
be set. If there is a valid data packet in the buffer, then the MCU clears the NACK bit and proceeds with
reading the data.
2.2.7.4.3 Isochronous In Transaction (CODEC as source and host PC as destination)
The steps to be followed for an isochronous in transaction are as follows:
1. MCU initializes one of the in endpoints as an in isochronous endpoint by programming the appropriate USB
endpoint configuration block. This entails programming the buffer size and the buffer base address for both
the X and Y buffers and the bytes per sample bits, setting the isochronous endpoint bit, enabling the
endpoint, and setting the NACK bit.
2. The MCU initializes one of the four DMA channels to support the isochronous in endpoint by programming
the appropriate DMA configuration registers.
3. During the current USB frame, the DMA proceeds with reading the data from the CODEC port interface and
storing the data in the X (or Y) endpoint buffer. At the end of the current USB frame, the DMA updates the
sample count in the data count byte then clears the X (or Y) buffer NACK bit to a 0. If a buffer overflow occurs,
the DMA will set the overflow bit in the endpoint configuration byte.
4. The host PC sends an iIn token packet addressed to the in endpoint. The UBM reads the X (or Y) buffer
data count byte to verify the NACK bit is cleared and to obtain the sample count of the new data packet.
The UBM reads the data packet from the X (or Y) endpoint buffer then transmits the data to the PC. At the
end of the USB transaction, the UBM sets the X (or Y) buffer NACK bit to a 1. Note that if a new data packet
has not been written to the buffer by the DMA, then the NACK bit will still be set to a 1 and the UBM will send
a null packet to the PC. Also, note that there is not an endpoint interrupt generated for isochronous
endpoints.
2.2.7.4.4 Isochronous In Transaction (MCU as source and host PC as destination)
The steps to be followed for an isochronous in transaction are as follows:
1. MCU initializes one of the in endpoints as an in isochronous endpoint by programming the appropriate USB
endpoint configuration block. This entails programming the buffer size and the buffer base address for both
the X and Y buffers and the bytes per sample bits, setting the isochronous endpoint bit, enabling the
endpoint, and setting the NACK bit.
2. The host PC sends an in token packet addressed to the in endpoint. The UBM reads the X (or Y) buffer data
count byte to verify the NACK bit is cleared and to obtain the sample count of the new data packet. The UBM
reads the data packet from the X (or Y) endpoint buffer then transmits the data to the PC. At the end of the
USB transaction, the UBM sets the X (or Y) buffer NACK bit to a 1. Note that if a new data packet has not
been written to the buffer by the MCU then the NACK bit will still be set to a 1 and the UBM will send a null
packet to the PC. Also, note that there is not an endpoint interrupt generated for isochronous endpoints.
2.2.8 Adaptive Clock Generator (ACG)
The adaptive clock generator is used to generate a programmable master clock output signal (MCLKO) that can be
used by the CODEC port interface and the CODEC device. The ACG can be used to generate the master clock for
the CODEC for USB asynchronous, synchronous, and adaptive modes of operation. However, for the USB
asynchronous mode of operation, an external clock can be used to drive the MCLKI signal of the TUSB3200. In this
scenario, the MCLKI signal would be used as the clock source for the CODEC port interface instead of the clock output
from the ACG.